AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 873

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32.6
32.6.1
32.6.1.1
32117C–AVR-08/11
Functional Description
USB General Operation
Initialization
After a hardware reset, the USBC is disabled. When enabled, the USBC runs in either device
mode or in host mode according to the ID detection.
If the USB_ID pin is not connected to ground and the pull-up is enabled, the USB_ID state bit in
the General Status register (USBSTA.ID) will be set and the device mode will be enabled.
If a low level is detected on the USB_ID pin, the USBSTA.ID bit will be cleared and the host
mode will be enabled.
Figure 32-2. General states
After a hardware reset, the USBC is in the Reset state. In this state:
After writing a one to USBCON.USBE, the USBC enters device or host mode (according to the
ID detection) in idle state.
Refer to
Refer to
• The module is disabled. The USBC Enable bit in the General Control register
• The module clock is stopped in order to minimize power consumption. The Freeze USB Clock
• The USB pad is in suspend mode.
• The internal states and registers of the device and host modes are reset.
• The USBSTA.ID bit and the VBUS Level bit (USBSTA.VBUS) reflect the states of the USB_ID
• The VBUS Level bit (USBSTA.VBUS) reflects the states of the USB_VBUS input pins.
• The OTG Pad Enable (OTGPADE), VBUS Polarity (VBUSPO), Freeze USB Clock (FRZCLK),
(USBCON.USBE) is reset.
bit in USBCON (USBCON.FRZCLK) is set.
and USB_VBUS input pins.
USBC Enable (USBE), USB_ID Pin Enable (UIDE), USBC Mode (UIMOD) in USBCON, and
the Low-Speed mode bit in the Device General Control register (UDCON.LS) can be written
to by software, so that the user can configure pads and speed before enabling the module.
These values are only taken into account once the module has been enabled and unfrozen.
Section 32.6.2
Section 32.6.3
for the basic operation of the device mode.
for the basic operation of the host mode.
Clock stopped:
FRZCLK = 1
Device
Macro off:
USBE = 0
USBE = 1
ID = 1
USBE = 0
Reset
USBE = 1
ID = 0
USBE = 0
USBE = 0
Host
RESET
HW
<any
other
state>
AT32UC3C
873