AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 1211

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

39.4.11.5
39.4.11.6
32117C–AVR-08/11
Error Reporting
Protected Reporting
The Service Access Bus may not be able to complete all accesses as requested. This may be
because the address is invalid, the addressed area is read-only or cannot handle byte/halfword
accesses, or because the chip is set in a protected mode where only limited accesses are
allowed.
The error bit is updated when an access completes, and is cleared when a new access starts.
What to do if the error bit is set:
A protected status may be reported during Shift-IR or Shift-DR. This indicates that the security
bit in the Flash Controller is set and that the chip is locked for access, according to
39.5.1.
The protected state is reported when:
What to do if the protected bit is set:
• During Shift-DR of an address: The new address is ignored. The SAB stays in address mode,
• During Shift-DR of read data: The read data is invalid. The SAB stays in data mode. Repeat
• During Shift-DR of write data: The write data is ignored. The SAB stays in data mode. Repeat
• During Shift-IR: The new instruction is selected. The last operation performed using the old
• During Shift-DR of an address: The previous operation failed. The new address is accepted.
• During Shift-DR of read data: The read operation failed, and the read data is invalid.
• During Shift-DR of write data: The previous write operation failed. The new data is accepted
• While polling with CANCEL_ACCESS: The previous access was cancelled. It may or may not
• After power-up: The error bit is set after power up, but there has been no previous SAB
• The Flash Controller is under reset. This can be due to the AVR_RESET command or the
• The Flash Controller has not read the security bit from the flash yet (This will take a a few
• The security bit in the Flash Controller is set.
• Release all active AVR_RESET domains, if any.
• Release the RESET_N line.
• Wait a few ms for the security bit to clear. It can be set temporarily due to a reset.
continue shifting the same instruction until the busy bit clears, or start shifting data. If shifting
data, you must be prepared that the data shift may also report busy.
so no data must be shifted. Repeat the address until the busy bit clears.
scanning until the busy bit clears.
scanning until the busy bit clears.
instruction did not complete successfully.
If the read bit is set, a read operation is started.
and a write operation started. This should only occur during block writes or stream writes. No
error can occur between scanning a write address and the following write data.
have actually completed.
instruction so this error can be discarded.
RESET_N line.
ms). Happens after the Flash Controller reset has been released.
AT32UC3C
Section
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