AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 253
AT32UC3C2256C
Manufacturer Part Number
AT32UC3C2256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C2256C
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
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- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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- Download datasheet (20Mb)
15. Flash Controller (FLASHC)
15.1
15.2
15.3
15.3.1
15.3.2
15.3.3
32117C–AVR-08/11
Features
Overview
Product Dependencies
Power Management
Clocks
Interrupt
Rev: 3.0.2.2
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The Flash Controller (FLASHC) interfaces the on-chip flash memory with the 32-bit internal HSB
bus. The controller manages the reading, writing, erasing, locking, and unlocking sequences.
In order to use this module, other parts of the system must be configured correctly, as described
below.
If the CPU enters a sleep mode that disables clocks used by the FLASHC, the FLASHC will stop
functioning and resume operation after the system wakes up from sleep mode.
The FLASHC has two bus clocks connected: One High Speed Bus clock (CLK_FLASHC_HSB)
and one Peripheral Bus clock (CLK_FLASHC_PB). These clocks are generated by the Power
Manager. Both clocks are enabled at reset, and can be disabled by writing to the Power Man-
ager. The user has to ensure that CLK_FLASHC_HSB is not turned off before reading the flash
or writing the pagebuffer and that CLK_FLASHC_PB is not turned off before accessing the
FLASHC configuration and control registers. Failing to do so may deadlock the bus.
The FLASHC interrupt request lines are connected to the interrupt controller. Using the FLASHC
interrupts requires the interrupt controller to be programmed first.
Controls flash block with dual read ports allowing staggered reads.
Supports 0 and 1 wait state bus access.
Allows interleaved burst reads for systems with one wait state, outputting one 32-bit word per
clock cycle.
32-bit HSB interface for reads from flash array and writes to page buffer.
32-bit PB interface for issuing commands to and configuration of the controller.
16 lock bits, each protecting a region consisting of (total number of pages in the flash block / 16)
pages.
Regions can be individually protected or unprotected.
Additional protection of the Boot Loader pages.
Supports reads and writes of general-purpose NVM bits.
Supports reads and writes of additional NVM pages.
Supports device protection through a security bit.
Dedicated command for chip-erase, first erasing all on-chip volatile memories before erasing
flash and clearing security bit.
AT32UC3C
253
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