AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 85

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8.5.4.1
8.5.4.2
8.5.4.3
8.5.4.4
32117C–AVR-08/11
Enabling a generic clock
Disabling a generic clock
Changing clock frequency
Generic clock implementation
OSCSEL
Figure 8-3.
A generic clock is enabled by writing a one to the CEN bit in GCCTRL to one. Each generic clock
can individually select a clock source by setting the OSCSEL bits. The source clock can option-
ally be divided by writing a one to DIVEN and the division factor to DIV, resulting in the output
frequency:
The generic clock can be disabled by writing a zero to CEN or entering a sleep mode that dis-
ables the PB clocks. In either case, the generic clock will be switched off on the first falling edge
after the disabling event, to ensure that no glitches occur. If CEN is written to zero, the bit will still
read as one until the next falling edge occurs, and the clock is actually switched off. When writ-
ing a zero to CEN, the other bits in GCCTRL should not be changed until CEN reads as zero, to
avoid glitches on the generic clock.
When the clock is disabled, both the prescaler and output are reset.
When changing generic clock frequency by writing GCCTRL, the clock should be switched off by
the procedure above, before being re-enabled with the new clock source or division setting. This
prevents glitches during the transition.
In AT32UC3C, the generic clocks are allocated to different functions as shown in
Table 8-2.
Clock number
f
GCLK
0
1
2
= f
SRC
Generic clock generation
Generic clock allocation
/
Function
USB clock (48 MHz)
CANIF
AST
(2*(DIV+1))
Divider
DIV
DIVEN
0
1
Sleep Controller
Mask
CEN
Name
GCLK_USBC
GCLK_CANIF
GCLK_AST
Generic Clock
AT32UC3C
Table
8-2.
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