AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 571
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AT32UC3C2256C
Manufacturer Part Number
AT32UC3C2256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C2256C
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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- Download datasheet (20Mb)
25.6.2
32117C–AVR-08/11
Receiver and Transmitter Control
Generator Register (BRGR). The resulting clock can be provided to the CLK pin to feed the
smart card clock inputs. This means that the CLKO bit can be set in MR.
This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio
register (FIDI). This is performed by the Sampling Divider, which performs a division by up to
2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user
must program the FI_DI_RATIO field to a value as close as possible to the expected value.
The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common
divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1).
Figure 25-4
and the ISO 7816 clock.
Figure 25-4. Elementary Time Unit (ETU)
After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit
in the Control Register (CR). However, the receiver registers can be programmed before the
receiver clock is enabled.
After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the
Control Register (CR). However, the transmitter registers can be programmed before being
enabled.
The Receiver and the Transmitter can be enabled together or independently.
At any time, the software can perform a reset on the receiver or the transmitter of the USART by
setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (CR).
The software resets clear the status flag and reset internal state machines but the user interface
configuration registers hold the value configured prior to software reset. Regardless of what the
receiver or the transmitter is performing, the communication is immediately stopped.
The user can also independently disable the receiver or the transmitter by setting RXDIS and
TXDIS respectively in CR. If the receiver is disabled during a character reception, the USART
waits until the end of reception of the current character, then the reception is stopped. If the
transmitter is disabled while it is operating, the USART waits the end of transmission of both the
current character and character being stored in the Transmit Holding Register (THR). If a time-
guard is programmed, it is handled normally.
ISO7816 I/O Line
ISO7816 Clock
shows the relation between the Elementary Time Unit, corresponding to a bit time,
on TXD
on CLK
ISO7816 Clock Cycles
FI_DI_RATIO
1 ETU
AT32UC3C
571
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