AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 303

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.6
17.6.1
17.6.2
17.6.3
17.7
17.7.1
32117C–AVR-08/11
Functional Description
Application Example
Bus Multiplexing
Static Memory Controller
SDRAM Controller
Hardware Interface
The EBI transfers data between the internal HSB bus (handled by the HMATRIX) and the exter-
nal memories or peripheral devices. It controls the waveforms and the parameters of the
external address, data and control busses and is composed of the following elements:
The EBI offers a complete set of control signals that share the 16(8)-bit data lines, the address
lines of up to 24 bits and the control signals through a multiplex logic operating in function of the
memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and
output control lines at a stable state while no external access is being performed. Multiplexing is
also designed to respect the data float times defined in the Memory Controllers. Furthermore,
refresh cycles of the SDRAM are executed independently by the SDRAMC without delaying the
other external memory controller accesses.
For information on the Static Memory Controller, refer to the Static Memory Controller Section.
Writing a one to the HMATRIX.SFR6.CS1A bit enables the SDRAM logic.
For information on the SDRAM Controller, refer to the SDRAM Section.
Table 17-4.
Pins name
Controller
DATA[7:0]
DATA[15:0]
ADDR[0]
ADDR[1]
ADDR[23:2]
NCS[0] - NCS[3]
• The Static Memory Controller (SMC)
• The SDRAM Controller (SDRAMC)
• A chip select assignment feature that assigns an HSB address space to the external devices
• A multiplex controller circuit that shares the pins between the different memory controllers
EBI Pins and External Static Devices Connections
8-bit Static
Device
A[23:2]
D[7:0]
A[0]
A[1]
CS
–
Pins of the Interfaced Device
2 x 8-bit
Devices
D[15:8]
A[22:1]
Static
D[7:0]
SMC
A[0]
CS
–
AT32UC3C
16-bit Static
Device
NBS0
D[15:8]
A[22:1]
D[7:0]
A[0]
CS
(2)
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