AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 1049

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

34.5.2
34.5.3
34.5.4
34.5.5
34.5.6
34.6
34.6.1
34.6.1.1
32117C–AVR-08/11
Functional Description
Power Management
Clocks
Interrupts
Peripheral Events
Debug Operation
Basic Operation
Enabling the QDEC
If the CPU enters a sleep mode that disables clocks used by the QDEC, the QDEC will stop
functioning and resume operation after the system wakes up from sleep mode.
The QDEC has two clocks connected: One Peripheral Bus clock (CLK_QDEC) and one generic
clock (GCLK_QDEC). These clocks are generated by the Power Manager. CLK_QDEC is
enabled at reset, and can be disabled in the Power Manager.
GCLK_QDEC is used for filtering in QDEC mode and is the timer clock in Timer Mode. It is a
generic clock generated by the Power Manager. The programmer must configure the Power
Manager to enable GCLK_QDEC. The GCLK_QDEC frequency must less than half the
CLK_QDEC clock frequency.
The QDEC interrupt request line is connected to the interrupt controller. Using the QDEC inter-
rupt requires the interrupt controller to be programmed first.
The QDEC peripheral events are connected via the Peripheral Event System. Refer to the
Peripheral Event System chapter for details.
When an external debugger forces the CPU into debug mode, the QDEC continues normal
operation; the timer is not frozen, but peripheral events are masked.
In OCD mode, the timer is not frozen and the events are masked. Reading the CAP register
does not clear the reminding of last capture event for the OVR interrupt.
If the QDEC is configured in a way that requires it to be periodically serviced by the CPU through
interrupts or similar, improper operation or data loss may result during debugging.
The QDEC peripheral events are masked during debug operation, unless the Run In Debug bit
in the Development Control Register is written to one and the bit corresponding to the QDEC is
written to one in the Peripheral Debug Register (PDBG). Please refer to the On-Chip Debug
chapter in the AVR32UC Technical Reference Manual, and the OCD Module Configuration sec-
tion, for details.
The QDEC is enabled by writing a one to the Clock Enable bit in the Control Register
(CTRL.CLKEN). This will also enable the internal CLK_QDEC_INT. This clock is generated from
GCLK_QDEC.
CLK_QDEC_INT is used in the filter blocks and for clocking the counter in Timer Mode. A soft-
ware trigger or peripheral event trigger is needed for CLK_QDEC_INT to start. The Clock Enable
bit in the Status Register (SR.CLKEN) indicates if the clock is running.
AT32UC3C
1049