AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 607

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.6.9.10
32117C–AVR-08/11
Node Action
During header transmission, the parity bits are computed and sent with the 6 least significant
bits of the IDCHR field of the LIN Identifier register (LINIR). The bits 6 and 7 of this register are
discarded.
During header reception, the parity bits of the identifier are checked. If the parity bits are wrong,
an Identifier Parity error occurs (see
IDCHR field are updated with the received Identifier. The bits 6 and 7 are stuck at 0.
During header transmission, all the bits of the IDCHR field of the LIN Identifier register (LINIR)
are sent on the bus.
During header reception, all the bits of the IDCHR field are updated with the received Identifier.
In function of the identifier, the node is concerned, or not, by the LIN response. Consequently,
after sending or receiving the identifier, the USART must be configured. There are three possi-
ble configurations:
This configuration is made by the field, Node Action (NACT), in the LINMR register (see
25.7.16).
Example: a LIN cluster that contains a Master and two Slaves:
• PARDIS = 0:
• PARDIS = 1:
• PUBLISH: the node sends the response.
• SUBSCRIBE: the node receives the response.
• IGNORE: the node is not concerned by the response, it does not send and does not receive
• Data transfer from the Master to the Slave 1 and to the Slave 2:
• Data transfer from the Master to the Slave 1 only:
• Data transfer from the Slave 1 to the Master:
• Data transfer from the Slave1 to the Slave2:
the response.
NACT(Master)=PUBLISH
NACT(Slave1)=SUBSCRIBE
NACT(Slave2)=SUBSCRIBE
NACT(Master)=PUBLISH
NACT(Slave1)=SUBSCRIBE
NACT(Slave2)=IGNORE
NACT(Master)=SUBSCRIBE
NACT(Slave1)=PUBLISH
NACT(Slave2)=IGNORE
NACT(Master)=IGNORE
NACT(Slave1)=PUBLISH
NACT(Slave2)=SUBSCRIBE
Section
25.6.3.8). Only the 6 least significant bits of the
AT32UC3C
Section
607