AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 1126

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

36.7.6
Name:
Access Type:
Offset:
Reset Value:
• CNVNB: Number of Conversions in a Sequence
• SRES: Resolution
• TRGSEL: Trigger Selection
• SHDYN: Sample and Hold Dynamic Mode
• OVSX2: Oversampling X2
• SOCB: Start of Conversion Behavior
32117C–AVR-08/11
31
23
15
7
-
-
-
-
The number of conversions to perform in the sequence is (CNVNB+1).
0: 12 bits.
1: 10 bits.
2: 8 bits.
3: Reserved.
0: Software.
1: Internal ADC timer.
2: Event controller source.
3: Continuous.
1: The SH dynamic mode,is enabled, a conversion takes two ADC clock cycles, SH is reseted on the first cycle.
0: The SH dynamic mode is disabled, a conversion takes a single ADC clock cycle.
1: The oversampling mode is enabled, a conversion takes two ADC clock cycles.
0: The oversampling mode is disabled, a conversion takes a single ADC clock cycle.
1: The SOCB mode is enabled, a single conversion is performed on a SOC event.
0: The SOCB mode is disabled, a complete sequence is performed on a SOC event.
Sequencer n Configuration Register
30
22
14
6
-
-
-
-
SEQCFGn
Read/Write
0x14 + n * 0x04
0x00000000
29
21
13
5
-
-
-
SRES
SHDYN
28
20
12
4
-
OVSX2
27
19
11
3
-
-
SOCB
26
18
10
2
-
-
CNVNB
HWLA
25
17
9
1
-
TRGSEL
AT32UC3C
SA
24
16
8
0
-
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