AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 1106

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

36.6.3
36.6.4
36.6.4.1
36.6.4.2
32117C–AVR-08/11
Power Reduction Modes
ADC Sequencer Operating Modes
General
Single-sequencer mode (cascaded mode)
Configuration bits acting on the power consumption of the digital and analog blocks are ADC
enable ( ADCEN) and Sleep Mode Selection (SLEEP) bits located in the CFG register:
Table 36-3.
Table 36-4.
Depending on the Start Of Conversion Behavior (SOCB) bit in the Sequencer Configuration
(SEQCFGx) register, the HOT start-up sequence will be performed before each conversion or
before each new conversion sequence. The ADC analog block is powered off when not used, it
needs 24 ADC clock cycles to wake-up. If start of conversion frequency is lower than
1/25.f(CkADC) then no conversion will be lost.
The ADC sequencer consists in two independent 8-state sequencers (SEQ0 and SEQ1) that
can also be cascaded together to form one 16-state sequencer (SEQ). The word “state” repre-
sents the number of auto-conversions that can be performed with the sequencer. In both cases,
the ADC has the ability to auto-sequence a series of conversions. This means that each time a
sequencer receives a start-of-conversion request, it can perform multiple conversions automati-
cally. For every sequencer conversion in dual-sequencer mode, any one of the available
sequencer 16 input channels can be selected through the analog MUX. In the same way, in sin-
gle-sequencer mode, any of the SEQ0 input channels can be selected. After conversion, the
digital value of the selected channel is stored in the appropriate result register (RESn). It is also
possible to sample the same channel multiple times, allowing the user to perform “over-sam-
pling”, which gives increased resolution over traditional single-sampled conversion results.
By setting the Single Sequencer Mode (SSMQ) bit in the CFG register, the two sequencers are
cascaded allowing a maximum of 16 successive measures among the SEQ0 16 analog inputs.
Figure 36-2
(SOC) request. The sequence of analog inputs to be measured is determined by the values of
(INPSEL0x, INNSEL0x) and (INPSEL1x, INNSEL1x) couples of registers. Each analog input is
selected by the analog multiplexer then sampled one by one every ADC clock cycle. In addition,
the conversion lasts (SRES / 2 + 3 - SHD) ADC clock cycles due to the ADC pipelined topology.
ADCEN
SLEEP
0
1
0
1
shows a sequence of 4 differential measures, initiated by the Start Of Conversion
Behavior
Digital controller dynamic activity is stopped (gated clocks)
All analog is powered off (reference sources, ADC, sample & hold)
Digital controller enabled
Analog references are switched on
The ADC block is powered on depending on the SLEEP bit
Behavior
Analog ADC block always powered on
Analog ADC block powered off after each conversion
Power Reduction Mode over the ADCEN Setting
Power Reduction Mode
AT32UC3C
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