AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 255

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32117C–AVR-08/11
The FLASHC can also operate in systems where the HSB bus clock period is faster than the
access speed of the flash memory. Wait state support and a read granularity of 64 bits ensure
efficiency in such systems.
Performance for systems with high clock frequency is increased since the flash internally is con-
figured as two separate banks of 32 bits. Each bank has its own read port. In 0ws mode, only
one of the two flash read ports is accessed. The other flash read port is idle. In 1ws mode, both
flash read ports are active. One read port reading the addressed word, and the other reading the
next sequential word.
The programmer can select the wait states required by writing to the FWS field in the Flash Con-
trol Register (FCR). It is the responsibility of the programmer to select a number of wait states
compatible with the clock frequency and timing characteristics of the flash memory.
In 0ws mode, no wait states are encountered on any flash read operations. In 1 ws mode, one
stall cycle is encountered on the first access in a single or burst transfer.
If the clock frequency allows, the user should use 0ws mode, because this gives the lowest
power consumption for low-frequency systems as only one flash read port is read. Using 1ws
mode has a power/performance ratio approaching 0ws mode as the clock frequency
approaches twice the max frequency of 0ws mode. Using two flash read ports use twice the
power, but also give twice the performance.
The Flash Controller address space is displayed in
address pw and the User page is reserved, and reading addresses in this space returns an
undefined result. The User page is permanently mapped to an offset of 0x0080 0000 from the
start address of the flash memory. The Factory page is permanently mapped to an offset of
0x0080 0200 from the start address of the flash memory.
Table 15-1.
Memory type
Main array
User
Factory Page
User page Addresses
Start address, byte sized
0
0x0080 0000
0x0080 0200
Size
pw bytes
w bytes
w bytes
Figure
15-1. The memory space between
AT32UC3C
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