AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 227
AT32UC3C2256C
Manufacturer Part Number
AT32UC3C2256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C2256C
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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14.4
14.5
14.5.1
14.5.2
14.5.3
14.5.4
14.5.5
32117C–AVR-08/11
I/O Lines Description
Product Dependencies
I/O Lines
Power Management
Clocks
Interrupts
Debug Operation
Table 14-1.
In order to use this module, other parts of the system must be configured correctly, as described
below.
Multiplexed I/O lines can be used as event generators. To generate a peripheral event from an
external source the source pin must be configured as an input pin by the I/O Controller. It is also
possible to trigger a peripheral event by driving these pins from registers in the I/O Controller, or
another peripheral output connected to the same pin.
If the CPU enters a sleep mode that disables clocks used by the PEVC, the PEVC will stop func-
tioning and resume operation after the system wakes up from sleep mode. Peripheral events do
not require CPU intervention, and are therefore available in sleep modes where the CPU sleeps.
The PEVC has two bus clocks connected: One Peripheral Bus clock (CLK_PEVC) and the sys-
tem RC oscillator clock (CLK_RCSYS). These clocks are generated by the Power Manager.
Both clocks are enabled at reset, and can be disabled by writing to the Power Manager.
CLK_RCSYS is used for glitch filtering.
PEVC can generate an interrupt request in case of trigger generation or trigger overrun. The
PEVC interrupt request lines are connected to the interrupt controller. Using the PEVC interrupts
requires the interrupt controller to be programmed first.
PEVC is frozen during debug operation, unless the Run In Debug bit in the Development Control
Register is set and the bit corresponding to the PEVC is set in the Peripheral Debug Register
(PDBG). Please refer to the On-Chip Debug chapter in the AVR32UC Technical Reference Man-
ual, and the OCD Module Configuration section, for details.
Pin Name
PAD_EVT[n]
I/O Lines Description
Pin Description
External Event Inputs
Type
Input
AT32UC3C
227
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