AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 1108

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

36.6.4.5
36.6.4.6
32117C–AVR-08/11
Sequencer start/stop mode
Sequencer free running-mode
Thanks to the Software Acknowledge bit (SA) in the SEQCFGx register, the behavior of
sequencer x at the end of a sequence can be configured.
Table 36-6.
The Sequencer x Overrun Error bit (OVRx) in SR register indicates that an overrun error
occurred in the sequencer x. This means that the RES0 register has not been read while a new
sequence is starting. Events such as end-of-sequence or end-of-conversion can be caught by
interrupt servicing or polling routines thanks to the SEOSx and SEOCx bits in the SR register.
Only SEQ0 has the free-running mode capability. In free-running mode the ADC continuously
converts analog values configured in the sequencer. In this mode, the sequence restarts auto-
matically after each end of sequence without waiting for the last conversion to finish. This mode
is configured by setting the Free Running Mode (FRM) bit in the CFG register. The conversion
sequence will start on the first SOC defined by the Trigger Selection (TRGSEL) field in the
SEQCFG0 register. In this mode only SEQ0 is running once triggered.
When converting at full speed the sequencer always wait for the last conversion to be finished to
rise the sequencer end of sequence status bit (EOS).
sequence running. When the third channel is sampled the sequencer has to wait for the pipeline
to be flushed. This takes SRES/2+3-SHD clock cycles. To avoid this you can run that sequence
in free running mode. Please refer to
waiting for the pipeline to be flushed but the user will have to read the converted value before it
is overwritten by a new conversion.
Figure 36-4. Not Using FRM and Converting at Full Speed
SA
0
1
Comment
The sequencer waits for software acknowledge.
Acknowledge is done by writing a 1 in the SEOSx bit of the SCR register.
The sequencer will restart automatically a new sequence on a new SOC.
Results will be overwritten if not processed.
Sequencer Start/Stop Mode
Figure
36-5. The sequencer will run the sequence without
Figure 36-4
shows a 3 conversions
AT32UC3C
1108