AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 816
AT32UC3C2256C
Manufacturer Part Number
AT32UC3C2256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C2256C
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Part Number
Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
Cirrus
Quantity:
48
Part Number:
AT32UC3C2256C-U
Manufacturer:
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20 000
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Part Number:
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Manufacturer:
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• FORMAT: I2S or TDM Format
Table 30-6.
• DATALENGTH: Data Word Length
Table 30-7.
• MODE: Mode
Table 30-8.
32117C–AVR-08/11
0
1
2
3
0
1
2
3
4
5
6
7
0
1
DATALENGTH
FORMAT
MODE
I2S
LJ
TDM
TDMLJ
SLAVE
MASTER
I
Left-justified format, stereo with IWS high for left channel, and MSB of sample starting on IWS edge
TDM format, with (NBCHAN+1) channels, IWS high at beginning of first channel, and MSB of sample starting one ISCK
period after IWS edge
TDM format, left-justified, with (NBCHAN+1) channels, IWS high at beginning of first channel, and MSB of sample
starting on IWS edge
Frame Format
Data Word Length
Mode
2
S format, stereo with IWS low for left channel, and MSB of sample starting one ISCK period after IWS edge
ISCK and IWS pin inputs used as Bit Clock and Word Select/Frame Sync.
Bit Clock and Word Select/Frame Sync generated by IISC from GCLK_IISC and output to ISCK and IWS pins.
GCLK_IISC is output as Master Clock on IMCK if MR.IMCKMODE is one.
32 bits
24 bits
20 bits
18 bits
16 bits
16 bits compact stereo
8 bits
8 bits compact stereo
Word Length
Left sample in bits 15 through 0 and right sample in bits 31 through 16 of the same word
Left sample in bits 7 through 0 and right sample in bits 15 through 8 of the same word
Description
Comments
Comments
AT32UC3C
816
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