AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 869

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32. USB Interface (USBC)
32.1
32.2
Table 32-1.
32.3
32117C–AVR-08/11
pipe/endpoint
Features
Overview
Block Diagram
...
0
1
2
6
Description of USB pipes/endpoints
Mnemonic
Rev: 2.1.0.14
•
•
•
•
•
•
•
•
•
•
The Universal Serial Bus interface (USBC) module complies with the Universal Serial Bus (USB)
2.0 specification, .
Each pipe/endpoint can be configured into one of several transfer types. It can be associated
with one or more memory banks (located inside the embedded system or CPU RAM) used to
store the current data payload. If two banks are used (“ping-pong” mode), then one bank is read
or written by the CPU (or any other HSB master) while the other is read or written by the USBC
core.
Table 32-1
PEP0
PEP1
PEP2
PEP6
The USBC interfaces a USB link with a data flow stored in the embedded ram (CPU or HSB).
The USBC requires a 48 MHz ± 0.25% reference clock, which is the USB generic clock. For
more details see
full-speed or a 1.5MHz low-speed bit clock from the received USB differential data, and to trans-
mit data according to full- or low-speed USB device tolerances. Clock recovery is achieved by a
digital phase-locked loop (a DPLL, not represented) in the USBC module, which complies with
the USB jitter specifications.
...
Compatible with the USB 2.0 specification
Supports full (12Mbit/s) and low (1.5Mbit/s) speed communication
Supports Embedded Host
7 physical pipes/endpoints in ping-pong mode
Flexible pipe/endpoint configuration and reallocation of data buffers in embedded RAM
Supports an infinite number of virtual pipes (alternate pipe)
Up to two memory banks per pipe/endpoint
Built-in DMA with multi-packet support through ping-pong mode
On-chip transceivers with built-in pull-ups and pull-downs
On-chip Embedded Host pad with a VBUS analog comparator
describes the hardware configuration of the USBC module.
1023 bytes
1023 bytes
1023 bytes
1023 bytes
Max. size
”Clocks” on page
...
available banks
872. The 48MHz clock is used to generate either a 12MHz
Number of
...
1
2
2
2
Control/Isochronous/Bulk/Interrupt
Control/Isochronous/Bulk/Interrupt
Control/Isochronous/Bulk/Interrupt
Control/Isochronous/Bulk/Interrupt
Type
...
AT32UC3C
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