AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 1114

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

36.6.10
36.6.11
36.6.12
36.6.13
32117C–AVR-08/11
Analog Reference
Conversion Range
Conversion Results
Start Of Conversion (SOC)
The following sources are available as analog reference (AREF) in the ADC. They are selected
through the Reference Source (RS) field in the CFG register:
When using an internal reference, it is recommended inserting a decoupling capacitor between
ADCREFP and ADCREFN externally (mandatory to get the full 12-bits precision). This means
that two pins will be dedicated to reference decoupling. If the pins are needed for other pur-
poses, the decoupling may be skipped giving a conversion accuracy of 10 bits.
It is also possible to force a differential reference by setting the CFG.EXREF bit. This will bypass
the CFG.RS selection setting and make the ADC use the differential ADCREFP/ADCREFN pin
pair voltage as reference.
The conversion amplitude range is given by the ADC acquisition mode and the reference
source:
Table 36-8.
If the Half Word Left Adjust (HWLA) bit in the SEQCFGx register is set, then the result will be left
adjusted on the 16 lower bits of the RESn register. Otherwise, results will be right-adjusted.
ADC transfer function:
All conversion results are signed in two's complement representation. Extra bits depending on
resolution and left adjust settings are padded with the sign bit. It means that if you read RESn
registers as a 32 bits register, the result will be correct.
ADC sequencers conversions can be triggered for each sequencer with the following sources:
Table 36-9.
Internal reference 1
Internal reference 2
External reference 1
External reference 2
Sequencer
SEQ0
SEQ1
• 1V internal voltage reference
• 0.6*VDDANA internal voltage reference
• Two external reference voltage (ADCREF0 or ADCREF1 over chip analog ground)
Reference
Source
RESn
Conversion Range vs. Reference
Trigger of Start Of Conversion
=
Conversion range
±1V
±0.6 * VDDANA
± min(3.5 V, VDDANA - 0.7)
± min(3.5 V, VDDANA - 0.7)
Internal timer
GAIN
-------------------------------------------------------------------------------------------------------- -
(SOCx)
*
*
×
(
V VREFP
(
V ADCIN p ( ) V ADCIN n ( )
(
(
) V VREFN
Internal
Timer
–
*
*
–
(
(
controller
)
)
Event
*
*
)
)
)
×
2
SRES
re-synchronized
Event controller
+
HWLA
*
*
×
(
16 SRES
AT32UC3C
–
)
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