AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 413

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21.6
21.6.1
21.6.2
32117C–AVR-08/11
Descriptor Mode
Setting Up and Using the Descriptors
Descriptor Organization
The Descriptor Mode (DM) performs a series of single transfers. Data describing the transfers to
be performed are written to memory by software, forming a queue of descriptors, each descrip-
tor describing a transfer to be performed.
Before being able to use the Descriptor Mode, the channel’s Descriptor Start Address (DSARx)
register must be initialized to point to the first descriptor in the queue. Thereafter, the Current
Descriptor Address Register (CDARx) must be initialized to the same value.
When the CR.CHxEN bit is written to one, hardware will read the first descriptor in the queue,
and perform the transfer described therein. When this transfer has finished, the hardware will
update the descriptor associated with the transfer, clearing the V bit in the descriptor data struc-
ture located in memory. Thereafter, the hardware will read the next descriptor in the queue. The
address of this descriptor is dependent on the L bit of the descriptor that just completed, see
Section
If the new descriptor has its V bit set, the transfer described by this descriptor will be performed.
When the transfer is complete, the descriptor will be written back to memory, with the V bit
cleared. Thereafter, the next descriptor will be read. This continues until a descriptor with a
cleared V bit is read. The queue is then empty, and all transfers described in the queue have
been performed. The CR.CHxEN bit will then be cleared, and the channel will become idle.
In order to restart the channel, the descriptor pointed to by the Current Descriptor Address Reg-
ister (CDARx) for the channel must be updated by writing to the appropriate memory locations.
Thereafter, the CHxEN bit must be written to one. This will cause the descriptor to be read into
the MDMA, and the transfer will start.
The descriptor list is implemented as a ring of descriptors placed in memory. The length of the
descriptor ring is programmable; the last descriptor in the ring has its L bit set, indicating that the
next element in the ring is at the address pointed to by the Descriptor Start Address Register
(DSARx).
Each descriptor consists of four words. When a descriptor is loaded into the MDMA, the first
three of these words are read into the appropriate registers, while the fourth word is discarded.
21.6.2.
AT32UC3C
413