AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 67

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

GeodeLink™ Inteface Unit Register Descriptions
4.2.2.2
MSR Address
Type
Reset Value
Ports that are not implemented return 0 (RSVD). Ports that are slave only return 11. (See Section 4.2.2.10 "SLAVE_ONLY"
on page 73 for slave only port status.) Master/slave ports return the values as stated.
AMD Geode™ GX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:16
15:14
13:12
11:10
Bit
9:8
7:6
5:4
3:2
1:0
Port Active Enable (PAE)
Name
RSVD
P0_PAE
P7_PAE
P6_PAE
P5_PAE
P4_PAE
P3_PAE
P2_PAE
P1_PAE
GLIU0: 10000081h
GLIU1: 40000081h
R/W
Boot Strap Dependent
RSVD
Description
Reserved. Write as read.
Port 0 (GLIU0: GLIU; GLIU1: GLIU) Port Active Enable.
00: OFF - Master transactions are disabled.
01: LOW - Master transactions limited to one outstanding transaction.
10: Reserved.
11: ON - Master transactions enabled with no limitations.
Port 7 (GLIU0: Not Used; GLIU1: Not Used) Port Active Enable. See bits [15:14] for
decode.
Port 6 (GLIU0: VP; GLIU1: Not Used) Port Active Enable. See bits [15:14] for decode.
Port 5 (GLIU0: GP; GLIU1: GIO) Port Active Enable. See bits [15:14] for decode.
Port 4 GLIU0: DC; GLIU1: GLPCI) Port Active Enable. See bits [15:14] for decode.
Port 3 (GLIU0: CPU Core; GLIU1: GLCP) Port Active Enable. See bits [15:14] for
decode.
Port 2 (GLIU0: Interface to GLIU1; GLIU1: Not Used) Port Active Enable. See bits
[15:14] for decode.
Port 1 (GLIU0: GLMC; GLIU1: GLIU1: Not Used) Port Active Enable. See bits [15:14]
for decode.
PAE Bit Descriptions
PAE Register Map
RSVD
P0_
PAE
PAE
P7_
PAE
P6_
9
P5_
PAE
8
31505E
7
P4_
PAE
6
5
PAE
P3_
4
3
PAE
P2_
2
1
P1_
PAE
0
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