AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 60

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

4.2.1.3
MSR Address
Type
Reset Value
The flags are set with internal conditions. The internal conditions are enabled if the corresponding EN bit is 0. If EN is 1, the
condition does not set the flag. Reading the FLAG bit returns the value; writing 1 clears the FLAG; writing 0 has no effect.
60
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:37
Bit
36
35
34
33
GLD SMI MSR (GLD_MSR_SMI)
Name
RSVD
STATCNT3_
ASMI_FLAG
STATCNT2_
ASMI_FLAG
STATCNT1_
ASMI_FLAG
STATCNT0_
ASMI_FLAG
GLIU0: 10002002h
GLIU1: 40002002h
R/W
00000000_00000001h
31505E
Description
Reserved. Write as read.
Statistic Counter 3 ASMI Flag. If high, records that an ASMI was generated due to a
Statistic Counter 3 (GLIU0 MSR 100000ACh, GLIU1 MSR 400000ACh) event. Write 1 to
clear; writing 0 has no effect. STATCNT3_ASMI_EN (bit 4) must be low to generate
ASMI and set flag.
Statistic Counter 2 ASMI Flag. If high, records that an ASMI was generated due to a
Statistic Counter 2 (GLIU0 MSR 100000A8h, GLIU1 MSR 400000A8h) event. Write 1 to
clear; writing 0 has no effect. STATCNT2_ASMI_EN (bit 3) must be low to generate
ASMI and set flag.
Statistic Counter 1 ASMI Flag. If high, records that an ASMI was generated due to a
Statistic Counter 1 (GLIU0 MSR 100000A4h, GLIU1 MSR 400000A4h) event. Write 1 to
clear; writing 0 has no effect. STATCNT1_ASMI_EN (bit 2) must be low to generate
ASMI and set flag.
Statistic Counter 0 ASMI Flag. If high, records that an ASMI was generated due to a
Statistic Counter 0 (GLIU0 MSR 100000A0h, GLIU1 MSR 400000A0h) event. Write 1 to
clear; writing 0 has no effect. STATCNT0_ASMI_EN (bit 1) must be low to generate
ASMI and set flag.
GLD_MSR_SMI Bit Descriptions
GLD_MSR_SMI Register Map
RSVD
RSVD
GeodeLink™ Inteface Unit Register Descriptions
AMD Geode™ GX Processors Data Book
9
8
7
6
5
4
3
2
1
0