AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 519

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

Instruction Set
AMD Geode™ GX Processors Data Book
PSUBD Subtract Dword With Wrap-Around
PSUBSB Subtract Byte Signed With Saturation
PSUBSW Subtract Word Signed With Saturation
PSUBUSB Subtract Byte Unsigned With Saturation
PSUBUSW Subtract Word Unsigned With Saturation
PSUBW Subtract Word With Wrap-Around
PUNPCKHBW Unpack High Packed Byte, Data to Packed Words
PUNPCKHDQ Unpack High Packed Dword, Data to Qword
PUNPCKHWD Unpack High Packed Word, Data to Packed Dwords
PUNPCKLBW Unpack Low Packed Byte, Data to Packed Words
PUNPCKLDQ Unpack Low Packed Dword, Data to Qword
PUNPCKLWD Unpack Low Packed Word, Data to Packed Dwords
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX
®
Instructions
Table 8-28. MMX
0FFA [11 mm1
mm2]
0FFA [mod mm r/m]
0FE8 [11 mm1
mm2]
0FE8 [mod mm r/m]
0FE9 [11 mm1
mm2]
0FE9 [mod mm r/m]
0FD8 [11 mm1
mm2]
0FD8 [11 mm reg]
0FD9 [11 mm1
mm2]
0FD9 [11 mm reg]
0FF9 [11 mm1
mm2]
0FF9 [mod mm r/m]
0F68 [11 mm1 mm2]
0F68 [11 mm reg]
0F6A [11 mm1
mm2]
0F6A [11 mm reg]
0F69 [11 mm1 mm2]
0F69 [11 mm reg]
0F60 [11 mm1 mm2]
0F60 [11 mm reg]
0F62 [11 mm1 mm2]
0F62 [11 mm reg]
0F61 [11 mm1 mm2]
0F61 [11 mm reg]
Opcode
®
MMX reg 1 [dword] <--- MMX reg 1 [dword] - MMX reg 2
[dword]
MMX reg [dword] <--- MMX reg [dword] - memory64 [dword]
MMX reg 1 [sign byte] <--- sat -- (MMX reg 1 [sign byte] sub-
tract MMX reg 2 [sign byte])
MMX reg [sign byte] <--- sat --- (MMX reg [sign byte] subtract
memory64 [sign byte])
MMX reg 1 [sign word] <--- sat --- (MMX reg 1 [sign word] -
MMX reg 2 [sign word])
MMX reg [sign word] <--- sat --- (MMX reg [sign word] -
memory64 [sign word])
MMX reg 1 [byte] <--- sat --- (MMX reg 1 [byte] - MMX reg 2
[byte])
MMX reg [byte] <--- sat --- (MMX reg [byte] - memory64 [byte])
MMX reg 1 [word] <--- sat --- (MMX reg 1 [word] - MMX reg 2
[word])
MMX reg [word] <--- sat --- (MMX reg [word] - memory64
[word])
MMX reg 1 [word] <--- (MMX reg 1 [word] - MMX reg 2 [word])
MMX reg [word] <--- (MMX reg [word] - memory64 [word])
MMX reg 1 [word] <--- {MMX reg 1 [high byte], MMX reg 2
[high byte]}
MMX reg [word] <--- {memory64 [high byte], MMX reg [high
byte]}
MMX reg 1 <--- MMX reg 1 [high dword], MMX reg 2 [high
dword]
MMX reg <--- {memory64 [high dword], MMX reg [high
dword]}
MMX reg 1 [dword] <--- MMX reg 1 [high word], MMX reg 2
[high word]
MMX reg [dword] <--- memory64 [high word], MMX reg [high
word]
MMX reg 1 [word] <--- MMX reg 1 [low byte], MMX reg 2 [low
byte]
MMX reg [word] <--- memory64 [low byte], MMX reg [low byte]
MMX reg 1 <--- MMX reg 1 [low dword], MMX reg 2 [low
dword]
MMX reg <--- memory64 [low dword], MMX reg [low dword]
MMX reg 1 [dword] <--- MMX reg 1 [low word], MMX reg 2
[low word]
MMX reg [dword] <--- memory64 [low word], MMX reg [low
word]
Instruction Set (Continued)
Operation
31505E
Clock Ct
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Notes
519