AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 523

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

Instruction Set
AMD Geode™ GX Processors Data Book
FPATAN Function Eval: Tan-1(y/x)
FPREM Floating Point Remainder
FPREM1 Floating Point Remainder IEEE
FPTAN Function Eval: Tan(x)
FRNDINT Round to Integer
FRSTOR Load FPU Environment and Register
FSAVE Save FPU Environment and Register
FNSAVE Save FPU Environment and Register
FSCALE Floating Multiply by 2n
FSIN Function Evaluation: Sin(x)
FSINCOS Function Eval.: Sin(x)& Cos(x)
FSQRT Floating Point Square Root
FST Store FPU Register
FSTP Store FPU Register, Pop
FBSTP Store BCD Data, Pop
FIST Store Integer FPU Register
FISTP Store Integer FPU Register, Pop
FSTCW Store FPU Mode Control Register
FNSTCW Store FPU Mode Control Register
FSTENV Store FPU Environment
FNSTENV Store FPU Environment
FSTSW Store FPU Status Register
FNSTSW Store FPU Status Register
FSTSW AX Store FPU Status Register to AX
FNSTSW AX Store FPU Status Register to AX
FSUB Floating Point Subtract
FSUBP Floating Point Subtract, Pop
FSUBR Floating Point Subtract Reverse
FSUBRP Floating Point Subtract Reverse, Pop
FPU Stack
64-bit Real
32-bit Real
FPU Stack
80-bit Real
64-bit Real
32-bit Real
32-bit Integer
16-bit Integer
64-bit Integer
32-bit Integer
16-bit Integer
Top of Stack
80-bit Register
64-bit Real
32-bit Real
Top of Stack
80-bit Register
64-bit Real
32-bit Real
FPU Instruction
Table 8-29. FPU Instruction Set (Continued)
D9 F3
D9 F8
D9 F5
D9 F2
D9 FC
DD [mod 100 r/m]
(9B)DD [mod 110 r/m]
DD [mod 110 r/m]
D9 FD
D9 FE
D9 FB
D9 FA
DD [1101 0 n]
DD [mod 010 r/m]
D9 [mod 010 r/m]
DB [1101 1 n]
DB [mod 111 r/m]
DD [mod 011 r/m]
D9 [mod 011 r/m]
DF [mod 110 r/m]
DB [mod 010 r/m]
DF [mod 010 r/m]
DF [mod 111 r/m]
DB [mod 011 r/m]
DF [mod 011 r/m]
(9B)D9 [mod 111 r/m]
D9 [mod 111 r/m]
(9B)D9 [mod 110 r/m]
D9 [mod 110 r/m]
(9B)DD [mod 111 r/m]
DD [mod 111 r/m]
(9B)DF E0
DF E0
DC [1110 1 n]
D8 [1110 0 n]
DC [mod 100 r/m]
D8 [mod 100 r/m]
DE [1110 1 n]
DC [1110 0 n]
D8 [1110 1 n]
DC [mod 101 r/m]
D8 [mod 101 r/m]
DE [1110 0 n]
Opcode
ST(1) <--- ATAN[ST(1) / TOS]; then pop TOS
TOS <--- Rem[TOS / ST(1)]
TOS <--- Rem[TOS / ST(1)]
TOS <--- TAN(TOS); then push 1.0 onto stack
TOS <--- Round(TOS)
Restore state
Wait, then save state
Save state
TOS <--- TOS
TOS <--- SIN(TOS)
temp <--- TOS;
TOS <--- SIN(temp); then
push COS(temp) onto stack
TOS <--- Square Root of TOS
ST(n) <--- TOS
M.DR <--- TOS
M.SR <--- TOS
ST(n) <--- TOS; then pop TOS
M.XR <--- TOS; then pop TOS
M.DR <--- TOS; then pop TOS
M.SR <--- TOS; then pop TOS
M.BCD <--- TOS; then pop TOS
M.SI <--- TOS
M.WI <--- TOS
M.LI <--- TOS; then pop TOS
M.SI <--- TOS; then pop TOS
M.WI <--- TOS; then pop TOS
Wait Memory <--- Control Mode Register
Memory <--- Control Mode Register
Wait Memory <--- Env. Registers
Memory <--- Env. Registers
Wait Memory <--- Status Register
Memory <--- Status Register
Wait AX <--- Status Register
AX <--- Status Register
ST(n) <--- ST(n) - TOS
TOS <--- TOS - ST(n
TOS <--- TOS - M.DR
TOS <--- TOS - M.SR
ST(n) <--- ST(n) - TOS; then pop TOS
TOS <--- ST(n) - TOS
ST(n) <--- TOS - ST(n)
TOS <--- M.DR - TOS
TOS <--- M.SR - TOS
ST(n) <--- TOS - ST(n); then pop TOS
×
2
(ST(1))
Operation
31505E
(or extended)
Sngle/Dbl
269 - 354
217 - 232
130 - 215
345 - 374
Clock Ct
53 - 208
53 - 208
13/54
1/4
1/4
1/6
1/6
1/6
1/6
1/6
1/6
1/6
1/6
1/6
1/6
12
19
19
19
82
3
1
1
6
1
1
6
4
3
6
4
3
1
1
1
1
1
1
1
Notes
1, 2
1, 2
3
2
2
2
1
3
3
3
2
2
2
2
2
2
2
2
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