AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 377

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

Video Processor Register Descriptions
6.8.4.3
FP Memory Offset 410h
Type
Reset Value
AMD Geode™ GX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:32
31:28
Bit
27
26
25
24
23
22
SP
Power Management (PM)
Name
RSVD (RO)
SP
PWR_SEQ_SEL
RSVD
D
P
PUB2
PUB1
R/W
00000000_00000002h
Description
Reserved (Read Only). Reads back as 0.
Spares. Read/write; no function.
Power Sequence Select. Selects whether to use internal or external power
sequence. The power sequence controls the order in which FP_VDDEN, the data and
control signals, and the backlight control signal DISP_EN become active during power
up, and inactive during power down.
0: Use internal power sequencing (timing is controlled by bits [24:18]).
1: Use external power sequencing
Must be written to 0.
Reserved. This bit should always be set to 0.
Display Off Control Source. Selects how DISPOFF# is controlled. Independent con-
trol may be used to disable the backlight to save power even if the panel is otherwise
ON.
0: DISPOFF# is controlled by with the power up/down sequence.
1: DISPOFF# is controlled independently of the power sequence.
Panel Power On. Selects whether the panel is powered down or up following the
power sequence mechanism.
0: Power down.
1: Power up.
Panel power up and down phase timing is dependent upon a programmable reference
clock. The reference clock is set to 14.3 MHz with the DIV field of the GLIU Device
Master Configuration MSR to obtain 32 ms or 128 ms power sequence delays.
Panel Power Up Phase Bit 2. Selects the amount of time from when VDD is enabled
to when the panel data signals are enabled.
0: 32 ms
1: 128 ms
Panel Power Up Phase Bit 1. Selects the time amount of from when the panel data
signals are enabled to when panel VEE is enabled.
0: 32 ms.
1: 128 ms.
PM Bit Descriptions
PM Register Map
HDEL
RSVD
VDEL
9
SP
8
31505E
7
6
5
4
3
2
1
377
0