AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 159

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

CPU Core Register Descriptions
If paging is enabled, the region properties can be further modified by the PCD and PWT flags in the page table entry. The
PCD flag is OR’d with the CD bit of the region properties, and the PWT bit is OR’d with the WT bit of the region properties.
A similar combination is performed during tablewalks using the PCD/PWT bits from CR3 for the DTE access and the
PCD/PWT bits from the DTE for the PTE access. The net effect is that the WC and WS flags may actually be used even for
a region that is marked cacheable if a page table mapping later forces it to be uncacheable. For regions that are write-com-
bined, the PWT flag in the page table can be used to force write-burstable properties for selected pages.
AMD Geode™ GX Processors Data Book
WS
Note: “x” indicates setting or clearing this bit has no effect.
1
0
1
WC
1
1
1
WT
0
1
1
WP
0
0
0
Table 5-18. Write Operations vs. Region Properties (Continued)
WA
0
0
0
CD
1
1
1
Description
Write-combined (uncacheable). Writes to the same cache line may be com-
bined. Multiple writes to the same byte results in a single write with the last
value specified. Write order is not preserved; ideal for use with frame buffers.
Write-serialize. Limit the number of outstanding writes to the value of the
WSREQ field in DM_CONFIG0_MSR (MSR 00001800h[46:44]).
Write-burstable (uncacheable). Writes to the same cache line are combined
as long as they are to increasing addresses and do not access a previously
written byte. Multiple writes to the same byte results in multiple bytes on the
bus. The semantics match write bursting on PCI and should therefore be suit-
able for accessing memory-mapped devices.
Write-burstable (uncacheable). Writes to the same cache line are combined
as long as they are to increasing addresses and do not access a previously
written byte. Multiple writes to the same byte results in multiple bytes on the
bus. The semantics match write bursting on PCI and should therefore be suit-
able for accessing memory-mapped devices.
Write-serialize. Limit the number of outstanding writes to the value of the
WSREQ field in DM_CONFIG0_MSR (MSR 00001800h[46:44]).
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