AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 234

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

6.4.2
6.4.2.1
GP Memory Offset 00h
Type
Reset Value
GP_DST_OFFSET is used to give a starting location for the destination of a BLT or vector in the frame buffer space. It con-
sists of three fields: the DST_OFFSET, DST_XLSBS, and DST_YLSBS. DST_OFFSET is a pointer, that when added to
the frame buffer base address, gives the memory address of the first byte of the BLT or vector. For a left-to-right direction
BLT or a vector, the address should be aligned to the least significant byte of the first pixel, since this is the leftmost byte.
For a right-to-left direction BLT, the address should be aligned to the most significant byte of the first pixel, since this is the
rightmost byte of the BLT. The address alignment must also be correct with respect to the pixel depth. In 32-bpp mode, the
address specified must be aligned to the least significant or most significant byte of a DWORD, depending upon BLT direc-
tion. Pixels may not straddle a DWORD boundary. In 16-bpp mode, the address specified must be aligned to a 16-bit
boundary. DST_XLSBS and DST_YLSBS are used to inform the hardware of the location of the pixel within the pattern
memory for pattern alignment.
234
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
YLSBS
31:29
28:26
25:24
DST_
23:0
Bit
Graphics Processor Configuration Registers
Destination Offset (GP_DST_OFFSET)
Name
DST_YLSBS
DST_XLSBS
RSVD
DST_OFFSET
XLSBS
DST_
R/W
00000000h
31505E
RSVD
Description
Destination Y LSBs. Indicates Y coordinate of starting pixel within pattern memory.
Destination X LSBs. Indicates X coordinate of starting pixel within pattern memory.
Reserved. Write as read.
Destination Offset. Offset from the frame buffer base address to the first destination
pixel.
GP_DST_OFFSET Bit Descriptions
GP_DST_OFFSET Register Map
DST_OFFSET
Graphics Processor Register Descriptions
AMD Geode™ GX Processors Data Book
9
8
7
6
5
4
3
2
1
0