AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 289

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

Display Controller Register Descriptions
6.6.7.4
DC Memory Offset 7Ch
Type
Reset Value
This register is provided to enable testability of the compressed line buffer (FIFO) RAM. Before it is accessed, the DIAG bit
in the DC_GENERAL_CFG register should be set high (DC Memory Offset 04h[28] = 1) and the DFLE bit should be set low
(DC Memory Offset 04h[0] = 0). Also, the CFRW bit in DC_GENERAL_CFG (DC Memory Offset 04h[29]) should be set
appropriately depending on whether a series of reads or writes is to be performed. After each write, the FIFO write pointer
automatically increments. After all write operations have been performed, set CFRW high to enable read addresses to the
FIFO and then a pair of reads of don't care data must be performed to load 64-bits of data into the output latch. Each sub-
sequent read contains the appropriate data that was previously written. After each pair of reads, the FIFO read pointer
automatically increments.
AMD Geode™ GX Processors Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:0
Bit
DC Compression FIFO Diagnostic (DC_CFIFO_DIAG)
Name
CFIFO_DATA
R/W
xxxxxxxxh
Description
Compressed Data FIFO Diagnostic Read or Write Data
DC_CFIFO_DIAG Bit Descriptions
DC_CFIFO_DIAG Register Map
CFIFO_DATA
9
8
31505E
7
6
5
4
3
2
1
289
0