AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 117

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

CPU Core Register Descriptions
5.5.2.11 BTB Data Test Register
MSR Address
Type
Reset Value
AMD Geode™ GX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:17
63:48
45:37
36:35
15:9
Bit
8:0
Bit
16
47
46
34
Name
RSVD
BTB_TST
RSVD
BTB_INDX
Name
RSVD
BTB_LRW (RO)
BTB_VAL
BTB_CTAG
BTB_ALSB
BTB_IB_SP
00001109h
R/W
0000xxxx_xxxxxxxxh
RSVD
Description
Reserved. Write as read.
BTB Test Mode Enable. Enables test mode access to the BTB.
0: BTB_TST disable.
1: BTB_TST enable.
Reserved. Write as read.
BTB Index. Address of one of the 512 BTB entries. The BTB_INDX auto-increments by
one each time the BTB Data Test register is accessed (read or write), and wraps back to
000 after the value of 1FFh is reached.
Description
Reserved. Write as read.
BTB Least Recently Written Bit (Read Only). Stores the LRW flag for the tag RAM line
containing the entry being accessed. It is set according to the LRW algorithm for write
accesses.
0: Way 1 was last written.
1: Way 0 was last written.
BTB Line Valid Bit.
0: BTB line is invalid.
1: BTB line is valid.
BTB Tag Compare Value. This value is used to determine a BTB hit for the entry. The
bits correspond to bits [18:10] of the linear instruction pointer.
BTB Address LSBs. Stores the two LSBs of the instruction pointer. The BTB can only
track one branch per four bytes. These bits are used to confirm that the instruction
decoder of the integer pipeline saw the branch that the BTB identified.
BTB Branch Instruction Spans Instruction Buffer Line Boundary. Determines if a
branch instruction crosses the 8-byte instruction buffer line boundary.
0: BTB branch instruction does not cross the instruction buffer line boundary.
1: BTB branch instruction crosses the instruction buffer line boundary.
BTB Address Test Bit Descriptions
BTB Data Test Bit Descriptions
BTB Data Test Register Map
BTB_TADD
BTB_CTAG
9
8
31505E
7
6
5
4
3
2
1
117
0