AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 430

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

6.12.1.4
MSR Address
Type
Reset Value
430
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:22
Bit
Bit
21
20
19
18
17
3
2
1
0
GLD Error MSR (GLD_MSR_ERROR)
Name
VPHE_SSMI_
EN
BME_ASMI_
EN
TARE_ASMI_
EN
MARE_ASMI_
EN
Name
RSVD (RO)
PARE_ERR_
FLAG
SYSE_ERR_
FLAG
RSVD (RO)
BME_ERR_
FLAG
TARE_ERR_
FLAG
RSVD
50002003h
R/W
00000000_000000037h
31505E
Description
Virtual PCI Header Event Synchronous SMI Enable. Write 0 to allow SSMI flag to be
set in selected GLIU response packets. I/O reads and writes to location CFCh may cause
an SSMI depending upon the configuration of this bit and the DEV bits in the PBUS reg-
ister (MSR 50002012h[31:0]). Writing 0 also enables flag (bit 19) to be set upon event.
Broken Master Event Asynchronous SMI Enable. Write 0 to enable a broken PCI bus
master event to generate an ASMI and to set flag (bit 18).
Target Abort Received Event Asynchronous SMI Enable. Write 0 to enable a target
abort received event to generate an ASMI and to set flag (bit 17).
Master Abort Received Event Asynchronous SMI Enable. Write 0 to enable a master
abort received event to generate an ASMI and to set flag (bit 16).
Description
Reserved (Read Only). Reserved for future use.
Parity Error Event Error Flag. If high, records an ERR occurred due to detection of a
PCI bus parity error. Write 1 to clear; writing 0 has no effect. PARE_ERR_EN (bit 5) must
be low to generate ERR and set flag. Additionally, the PS_ERR_EN bit (MSR
50002010h[31]) must be set to enable this event.
System Error Event Error Flag. If high, records an ERR occurred due to detection of a
PCI bus system error. Write 1 to clear; writing 0 has no effect. SYSE_ERR_EN (bit 4)
must be low to generate ERR and set flag. Additionally, the PS_ERR_EN bit (MSR
50002010h[31]) must be set to enable this event.
Reserved (Read Only). Reads return 0.
Broken Master Event Error Flag. If high, records an ERR occurred due to detection of a
broken PCI bus master. Write 1 to clear; writing 0 has no effect. BME_ERR_EN (bit 2)
must be low to generate ERR and set flag. Additionally, the BM_ERR_EN bit (MSR
50002010h[30]) must be set to enable this event.
Target Abort Received Event Error Flag. If high, records an ERR occurred due to the
reception of a target abort on PCI. Write 1 to clear; writing 0 has no effect.
TARE_ERR_EN (bit 1) must be low to generate ERR and set flag. Additionally, the
TAR_ERR_EN bit (MSR 50002010h[29]) must be set to enable this event.
GLD_MSR_ERROR Bit Descriptions
GLD_MSR_ERROR Register Map
GLD_MSR_SMI Bit Descriptions
RSVD
GeodeLink™ PCI Bridge Register Descriptions
RSVD
AMD Geode™ GX Processors Data Book
9
8
7
6
5
4
3
2
1
0