AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 516

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

516
PCMPGTD Pack Compare Greater Than Dword
PCMPGTW Pack Compare Greater Than Word
PEXTRW Extract Word into Integer Register
Register 32, MMX Register 2 imm8
PINSRW Insert Word from Integer Register
MMX Register, Register 32 imm8
MMX Register, Memory 16, imm8
PMADDWD Packed Multiply and Add
PMAXSW Packed Maximum Signed Word
PMAXUB Packed Maximum Unsigned Byte
PMINSW Packed Minimum Signed Word
MMX Register 2 to MMX Register 1
Memory with MMX Register
MMX Register 2 to MMX Register 1
Memory with MMX Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 1 with MMX Register 2
MMX Register with Memory64
MMX Register 1 with MMX Register 2
MMX Register with Memory64
MMX Register 1with MMX Register 2
MMX
®
Instructions
31505E
Table 8-28. MMX
0F66 [11 mm1 mm2]
0F66 [mod mm r/m]
0F65 [11 mm1 mm2]
0F65 [mod mm r/m]
0FC5 [11 reg mm] #
0FC4 [11 mm1 reg]
#
0FC4 [mod mm r/m]
#
0FF5 [11 mm1
mm2]
0FF5 [mod mm r/m]
0FEE [11 mm1
mm2]
0FEE [mod mm r/m]
0FDE [11 mm1
mm2]
0FDE [mod mm r/m]
0FEA [11 mm1
mm2]
Opcode
®
MMX reg 1 [dword] <--- FFFF FFFFh --- if MMX reg 1 [dword]
> MMX reg 2 [dword]
MMX reg 1 [dword]<--- 0000 0000h ---if MMX reg 1
[dword]NOT > MMX reg 2 [dword]
MMX reg [dword] <--- FFFF FFFFh --- if memory[dword] >
MMX reg [dword]
MMX reg [dword] <--- 0000 0000h --- if memory[dword] NOT
> MMX reg [dword]
MMX reg 1 [word] <--- FFFFh --- if MMX reg 1 [word] > MMX
reg 2 [word]
MMX reg 1 [word]<--- 0000h --- if MMX reg 1 [word] NOT >
MMX reg 2 [word]
MMX reg [word] <--- FFFFh --- if memory[word] > MMX reg
[word]
MMX reg [word] <--- 0000h --- if memory[word] NOT > MMX
reg [word]
Reg 32 [high word] <--- 0000
reg32 [low word] <--- MMX reg [windex0 (imm8)]
tmp1 <--- 0
tmp1 [windex0 (imm8)] <--- reg 32 [low word]
tmp2 <--- MMX reg
tmp2 [windex0 (imm8)] <--- 0
MMX reg <--- tmp 1 Logic OR tmp2
temp1 <--- 0
tmp1 [windex0 (imm8)] <--- Memory 16
tmp2 <--- MMX reg
tmp2 [windex0 (imm8)] <--- 0
MMX reg <--- tmp1 Logic OR tmp2 [windex 0 (imm8)]
MMX reg 1 [low dword] <--- (MMX reg 1 [low dword] * MMX
reg 2 [low sign word] + (MMX reg 1 [low dword] * MMX reg2
[high sign word]
MMX reg 1 [high dword] <--- (MMX reg 1 [high dword] * MMX
reg 2 [low sign word] + (MMX reg 1 [high dword] * MMX reg2
[high sign word]
MMX reg 1 [low dword] <--- (memory [low dword] * MMX reg
[low sign word] + (memory1 [low dword] * MMX reg [high sign
word])
MMX reg 1 [high dword] <--- (memory [higi dword] * MMX reg
[low sign word] + (memory1 [high dword] * MMX reg [high sign
word])
MMX reg 1 [word] <--- MMX reg 1 [word] --- if (MMX reg 1
[sign word]
MMX reg 1 [word] <--- MMX reg 2 [word] --- if (MMX reg 1
[sign word] NOT
MMX reg [word] <--- MMX reg [word] --- if (MMX reg [sign
word]
[word] --- if (MMX reg [sign word] NOT
word]
MMX reg 1 [byte] <--- MMX reg 1 [byte] --- if (MMX reg 1 [byte]
>
MMX reg 1 [byte] <--- MMX reg 2 [byte] --- if (MMX reg 1 [byte]
NOT
MMX reg [byte] <--- MMX reg [byte] --- if (MMX reg [byte]
Memory64 [byte])
MMX reg [byte] <--- Memory64 [byte] --- if (MMX reg [byte]
NOT
MMX reg 1 [word] <--- MMX reg 1 [word] --- if (MMX reg 1
[sign word]
MMX reg 1 [word] <--- MMX reg 2 [word] --- if (MMX reg 1
[sign word] NOT
Instruction Set (Continued)
MMX reg 2 [byte]0
>
>
>
Memory64 [byte])
MMX reg 2 [byte])
Memory64 [word]) MMX reg [word] <--- Memory64
>
<
MMX reg 2 [sign word])
MMX reg 2 [sign word])
>
<
MMX reg 2 [sign word]
MMX reg 2 [sign word])
Operation
AMD Geode™ GX Processors Data Book
>
Memory64 [sign
>
Clock Ct
Instruction Set
2
2
2
2
1
2
2
2
2
2
2
2
2
2
Notes