AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 420

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

6.11.5
The PCI Arbiter block determines which PCI master is
granted permission to initiate data transfer on the PCI bus.
6.11.5.1
The PCI Arbiter block features are:
• Support for three external PCI masters and Host Bridge
• Request #2 is reserved for use by the South Bridge,
• Host Bridge master priority can be controlled via a
• Support for fixed priority scheme, rotation priority
• A priority rotation method based on priority usage
• Configurable request masking on all request lines in
• Broken master disable (REQ#0,1).
• Parking Policy. When this function is enabled, the arbiter
• Preemption. When this function is enabled, GNT# may
• Insert Idle. When this function is enabled, the arbiter
Figure 6-31 on page 421 is a top block diagram for the PCI
Arbiter block. It shows how to enable/disable the arbiter.
This function is controlled by the EA bit of the PCI Arbiter
Control register (MSR 50002011h [2]). When this bit is set
to 0 (default), request lines from masters are supplied to
the PCI Arbiter module. The arbiter then calculates and
asserts grant lines according to priority. If this bit is set to 1,
REQ#[2:1] are forced to be high internally, and REQ#[0]
and GNT#[0] act as EXT_GNT# and EXT_REQ# respec-
tively. The I/O cells for GNT#[2:1] are disabled (high
impedance). The next section describes in detail how to
implement an external arbiter.
420
master.
which requires higher priority.
programmable counter that allows 1-8 External PCI
grants to occur before the CPU can regain top priority
again.
scheme or hybrid of the two.
supporting 8 priority permutation to avoid “live-lock”
conditions.
response to a retry termination. Note that request
masking is automatically disabled whenever there is
only one active request.
parks the PCI bus on the last granted master. Otherwise
the arbiter always parks on Geode GX processor.
be deasserted before REQ# is deasserted.
always insert 1 clock idle cycle, that is all GNT# are
high. This function may be desirable when implementing
a slave arbiter.
PCI Arbiter
Overview
31505E
Figure 6-32 on page 422 is a functional block diagram for
the PCI Arbiter module. The request lines come into the
PCI Arbiter module. This request vector flows through the
request masking logic which is controlled by the Retry
Masking Timer and the Broken Master Detection.
The masked request lines then get sorted into priority order
by the Request Priority Permuter, which has the current
rotation priority (ARB_Priority[2:0]) as control input. PRCM,
FPVEC,
50002011h[26:24, 18:16, 5:3, 11:9] respectively) control
the Priority Rotation State Machine and output the current
rotation priority ARB_Priority[2:0]). The actual arbitration is
performed in the Arbitration Priority Selector, resulting in
the assertion of one of the grant outputs. The grant lines
are then “sorted” by the Grant Priority Permuter to map the
output of the Arbitration Priority Selector into the Grant
Output register and onto the correct PCI bus grant lines.
The Retry Masking Timer provides the ability to mask off a
given request line following a retry to that master for 8, 16,
32 or 64 PCI clock cycles. There are individual masking
timers for each request line and masking can be individu-
ally programmed for each request line.
The Broken Master Detection watches the REQ#, GNT#
line and PCI Bus status. When the granted PCI master
waits 16 or more PCI clock cycles before asserting
FRAME#, the arbiter masks off the request line from that
PCI master. This function can be disabled by setting the
BMD bit (MSR 50002011h[1]). After the arbiter detects bro-
ken master and masks off its request line, it can still be
cancelled by setting and clearing the BMD bit. This function
is not applied to the CPU (CPUREQ) and South Bridge
(REQ2#).
The Request Priority Permuter and the Grant Priority Per-
muter are based on the binary decision tree of Figure 6-33
on page 423 in which each bit of the ARB_PRIORITY[2:0]
vector controls one of the binary decisions of the tree. Note
that at the top of the tree, a decision between the CPU and
the external PCI masters as a group is being made. At first
glance, this may appear to give the CPU too high a priority,
but by adjusting the algorithm by CPU Priority Counter,
there is significant flexibility in setting the priority of the
CPU request. REQ2#, intended for use by the South
Bridge, is set apart from the other two requests. The
SBCTR (MSR Address 50002011h[5:3]) specifically con-
trols its priority relative to the other two requests
(REQ[1:0]#. Table 6-64 on page 422 enumerates the prior-
ity encoding defined by the decision tree.
CPCTR,
AMD Geode™ GX Processors Data Book
and
SBCTR
GeodeLink™ PCI Bridge
(MSR
Address