AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 503

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

Instruction Set
AMD Geode™ GX Processors Data Book
ICEBP Call Debug Exception Handler
IDIV Integer (Signed) Divide
IMUL Integer (Signed) Multiply
IN Input from I/O Port
INC Increment by 1
INS Input String from I/O Port
INT i Software Interrupt
INT 3 Breakpoint Software Interrupt
INTO Overflow Software Interrupt
INVD Invalidate Cache
INVLPG Invalidate TLB Entry
IRET Interrupt Return
JB/JNAE/JC Jump on Below/Not Above or Equal/Carry
Accumulator by Register/Memory
Accumulator by Register/Memory
Register with Register/Memory
Register/Memory with Immediate to Register2
Fixed Port
Variable Port
Register/Memory
Register (short form)
Protected Mode:
-Interrupt or Trap to Same Privilege
-Interrupt or Trap to Different Privilege
-16-bit Task to 16-bit TSS by Task Gate
-16-bit Task to 32-bit TSS by Task Gate
-16-bit Task to V86 by Task Gate
-16-bit Task to 16-bit TSS by Task Gate
-32-bit Task to 32-bit TSS by Task Gate
-32-bit Task to V86 by Task Gate
-V86 to 16-bit TSS by Task Gate
-V86 to 32-bit TSS by Task Gate
-V86 to Privilege 0 by Trap Gate/Int Gate
Real Mode
Protected Mode:
-Within Task to Same Privilege
-Within Task to Different Privilege
-16-bit Task to 16-bit Task
-16-bit Task to 32-bit TSS
-16-bit Task to V86 Task
-32-bit Task to 16-bit TSS
-32-bit Task to 32-bit TSS
-32-bit Task to V86 Task
8-bit Displacement
Full Displacement
Divisor:
Multiplier:
Multiplier:
Multiplier:
If OF==0
If OF==1 (INT 4)
Byte
Word
Doubleword
Instruction
Byte
Word
Doubleword
Word
Doubleword
Byte
Word
Doubleword
Table 8-26. Processor Core Instruction Set (Continued)
F1
F [011w] [mod 111 r/m]
F [011w] [mod 101 r/m]
0F AF [mod reg r/m]
6 [10s1] [mod reg r/m] ###
E [010w] #
E [110w]
F [111w] [mod 000 r/m]
4 [0 reg]
6 [110w]
CD #
CC
CE
0F 08
0F 01 [mod 111 r/m]
CF
72 +
0F 82 +++
Opcode
(Reg/Cache Hit)
Mode
Real
Clock Count
INT
30
16
24
40
10
23
21
10
3
4
7
4
7
4
4
7
7
7
1
1
4
7
9
1
1
37-215
Prot’d
Mode
45-82
10/24
7/21
7/21
184
190
124
187
193
127
187
193
INT
169
175
109
172
178
112
16
24
40
33
55
64
10
20
39
3
4
7
4
7
4
4
7
1
1
4
7
1
1
O D I
F F F F F F F F F
-
-
x
-
x
-
-
-
-
x
-
-
-
-
-
-
-
-
-
-
x
-
x
-
-
-
-
-
x
-
-
x
-
31505E
T S Z A P C
0 -
-
-
-
-
-
0 -
-
-
x
-
Flags
x
x
-
x
-
-
-
x
-
-
x
x
-
x
-
-
-
-
x
-
-
u u -
u u x
-
x
-
-
-
-
x
-
-
-
x
-
-
-
-
x
-
-
-
-
-
-
-
-
x
-
Mode
Real
b,e
b,e
b,c
b,c
b
b
b
t
Notes
Prot’d
g,h,j,k,
Mode
g,j,k,r
g,i,k,r
g,i,k,r
h,m
e,h
m
h
h
r
r
t
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