AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 437

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

GeodeLink™ PCI Bridge Register Descriptions
6.12.2.2
MSR Address
Type
Reset Value
AMD Geode™ GX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:50
46:43
38:35
31:27
26:24
Bit
49
48
47
42
41
40
39
34
33
32
RSVD
PCI Arbiter Control (ARB)
Name
RSVD (RO)
BM1 (RO)
BM0 (RO)
CPRE
RSVD (RO)
PRE2
PRE1
PRE0
CRME
RSVD (RO)
RME2
RME1
RME0
RSVD (RO)
PRCM
50002011h
R/W
00000000_00000000h
PRCM
RSVD
Description
Reserved (Read Only). Reads return 0.
Broken Master 1 (Read Only). Indicates when a broken master is attached to REQ1#.
This bit is set when the arbiter detects that the PCI bus master attached to REQ1# has
not asserted FRAME# within 16 PCI clock edges after being granted the PCI bus. This bit
is cleared by setting BMD (bit 1) to 1.
Broken Master 0 (Read Only). Indicates when a broken master is attached to REQ[0]#.
This bit is set when the arbiter detects that the PCI bus master attached to REQ[0]# has
not asserted FRAME# within 16 PCI clock edges after being granted the PCI bus. This bit
is cleared by setting BMD (bit 1) to 1.
CPU Preemption Enable. When set to 1, the CPU’s PCI grant may be de-asserted
before the CPU’s request is de-asserted.
Reserved (Read Only). Reads return 0.
Preemption Enable 2. When set to 1, GNT2# may be de-asserted before REQ2# is de-
asserted.
Preemption Enable 1. When set to 1, GNT1# may be de-asserted before REQ1# is de-
asserted.
Preemption Enable 0. When set to 1, GNT0# may be de-asserted before REQ0# is de-
asserted.
CPU Retry Mask Enable. When set to 1, CPU requests are masked following a retry ter-
mination of a PCI bus cycle initiated by the host PCI bridge master.
Reserved (Read Only). Reads return 0.
Retry Mask Enable 2. When set to 1, REQ2# is masked following a retry termination of a
cycle initiated by that master.
Retry Mask Enable 1. When set to 1, REQ1# is masked following a retry termination of a
cycle initiated by that master.
Retry Mask Enable 0. When set to 1, REQ0# is masked following a retry termination of a
cycle initiated by that master.
Reserved (Read Only). Reserved for future use.
Priority Rotation Control Mask. When these bits are set to 000, all of the arbiter priority
vector bits are allowed to rotate. When these bits are set to 111, all of the arbiter priority
vector bits are fixed to the values in the Fixed Priority Vector (FPVEC) field (bits 18:16]).
Any other value results in a hybrid priority scheme, where the arbiter priority vector bits
corresponding to the mask bits set to 1 are fixed to the values in the FPVEC and all other
bits are allowed to rotate.
RSVD
ARB Bit Definitions
ARB Register Map
FPVEC
RSVD
RSVD
SBCTR
9
8
31505E
7
RMT
6
RSVD
5
CPCTR
4
3
2
1
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