AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 395

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

GeodeLink™ Control Processor Register Descriptions
6.10.1.4
MSR Address
Type
Reset Value
AMD Geode™ GX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:36
31:4
Bit
35
34
33
32
3
2
1
GLD Error MSR (GLD_MSR_ERROR)
Name
RSVD
SYSPLL_ERR_
FLAG
DOTPLL_ERR_
FLAG
SIZE_ERR_FLAG
UNEXP_TYPE_
ERR_FLAG
RSVD
SYSPLL_ERR_EN
DOTPLL_ERR_EN
SIZE_ERR_EN
4C002003h
R/W
00000000_00000000h
Description
Reserved. Write as read.
System PLL Error Flag. If high, records that an ERR occurred due to the system
PLL lock signal being active when POR was inactive. Write 1 to clear; writing 0 has
no effect. SYSPLL_ERR_EN (bit 3) must be low to generate ERR and set flag.
Dot Clock PLL Error Flag. If high, records that an ERR occurred due to the DOT-
CLK PLL lock signal being active when POR was inactive. Write 1 to clear; writing 0
has no effect. DOTPLL_ERR_EN (bit 2) must be low to generate ERR and set flag.
Size Error Flag. If high, records that the GLIU1 interface detected a read or write of
more than 1 data packet (size = 16 bytes or 32 bytes). If a response packet is
expected, the EXCEPTION bit is set; in all cases the asynchronous error signal is
set. Write 1 to clear; writing 0 has no effect. SIZE_ERR_EN (bit 1) must be low to
generate ERR and set flag.
Unexpected Type Error Flag. An unexpected type was sent to the GLCP GLIU1
interface (start request with BEX type, snoop, PEEK_WRITE, DEBUG_REQ, or
NULL type). If a response packet is expected, the EXCEPTION bit is set; in all cases
the asynchronous error signal is set. Writing a 1 clears the error, writing a 0 leaves
unchanged.
Reserved. Write as read.
System PLL Error Enable. Write 0 to enable the ERR signal if the system PLL lock
signal is active when POR is inactive and set flag (bit 35).
Dot Clock PLL Error Enable. Write 0 to enable the ERR signal if the DOTCLK PLL
lock signal is active when POR is inactive and set flag (bit 34)
Size Error Enable. Write 0 to enable the ERR signal if the GLIU1 interface detects a
read or write of more than 1 data packet and set flag (bit 33).
GLD_MSR_ERROR Bit Descriptions
GLD_MSR_ERROR Register Map
RSVD
RSVD
9
8
31505E
7
6
5
4
3
2
1
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