AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 16

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

2.1.2
The Memory Management Unit (MMU) translates the linear
address supplied by the Integer Unit into a physical
address to be used by the Cache and TLB Subsystem and
the Bus Controller Unit. Memory management procedures
are x86-compatible, adhering to standard paging mecha-
nisms.
The MMU also contains a load/store unit that is responsible
for scheduling cache and external memory accesses. The
load/store unit incorporates two performance-enhancing
features:
• Load-store reordering that gives memory reads
• Memory-read bypassing that eliminates unnecessary
2.1.3
The Cache and TLB (Transaction Look-aside Buffer)Sub-
system of the CPU Core supplies the integer pipeline with
instructions, data, and translated addresses (when neces-
sary). To support the efficient delivery of instructions, the
subsystem has a single clock access 16 KB 4-way set
associative instruction cache and an 8-entry fully associa-
tive TLB. The TLB performs necessary address transla-
tions when in protected mode. For data, there is a 16 KB 4-
way set associative writeback cache, and an 8-entry fully
associative TLB. When there is a miss to the instruction or
data TLBs, there is a second level unified (instruction and
data) 64-entry 2-way set associative TLB that takes an
additional clock to access. When there is a miss to the
instruction or data caches or the TLB, the access must go
to the GeodeLink Memory Controller (GLMC) for process-
ing. Having both an instruction and a data cache and their
associated TLBs improves overall efficiency of the Integer
Unit by enabling simultaneous access to both caches.
2.1.4
The Bus Controller Unit provides a bridge from the Geode
GX processor to the GeodeLink Interface Unit. When exter-
nal memory access is required, due to a cache miss, the
physical address is passed to the Bus Controller Unit,
which translates the cycle to a GeodeLink cycle.
2.1.5
The Floating Point Unit (FPU) is a pipelined arithmetic unit
that performs floating point operations as per the IEEE 754
standard. The instruction sets supported are x87, MMX,
and 3DNow! technology. The FPU is a pipelined machine
with dynamic scheduling of instructions to minimize stalls
due to data dependencies. It performs out of order execu-
tion and register renaming. It is designed to support an
instruction issue rate of one per clock from the integer core.
The datapath is optimized for single precision arithmetic.
Extended precision instructions are handled in microcode
and require multiple passes through the pipeline. There is
16
required by the integer unit a priority over writes to
external memory.
memory reads by using valid data from the execution
unit.
Memory Management Unit
Cache and TLB Subsystem
Bus Controller Unit
Floating Point Unit
31505E
an execution pipeline and a load/store pipeline. This allows
load/store operations to execute in parallel with arithmetic
instructions.
2.2
The GeodeLink Control Processor (GLCP) is responsible
for reset control, macro clock management, and debug
support provided in the Geode GX processor. It contains
the JTAG interface and the scan chain control logic. It sup-
ports chip reset, including initial PLL control and program-
ming and runtime power management macro clock control.
The JTAG support includes a Tap Controller that is IEEE
1149.1 compliant. CPU control can be obtained through
the JTAG interface into the TAP Controller, and all internal
registers, including CPU Core registers, can be accessed.
In-circuit emulation (ICE) capabilities are supported
through this JTAG and Tap Controller interface.
2.3
Together, the two GeodeLink Interface Units (GLIU0 and
GLIU1) make up the internal bus derived from the
GeodeLink architecture. GLIU0 connects six high speed
modules together with a seventh link to GLIU1 that con-
nects to the three lower speed modules. (Refer to Figure 1-
1 on page 11 for the internal signal connections.)
2.4
The GeodeLink Memory Controller (GLMC) is the memory
source for all memory needs in a typical Geode GX proces-
sor-based system. The GLMC supports a memory data
bus width of 64 bits.
The GLMC supports up to 1 GB of memory:
• 111 MHz 222 MT/S for DDR (Double Data Rate)
The modules that need memory are the CPU Core, Graph-
ics Processor, Display Controller, and TFT Controller.
Because the GLMC supports memory needs for both the
CPU Core and the display subsystem, the GLMC is classi-
cally called a UMA (Unified Memory Architecture) memory
subsystem.
Up to four banks, with eight devices maximum in each
bank, of SDRAM are supported, with up to 256 MB in each
bank. Four banks means that one or two DIMM or
SODIMM modules can be used in a Geode GX processor-
based system. Some memory configurations have addi-
tional restrictions on maximum device quantity.
GeodeLink™ Control Processor
GeodeLink™ Interface Units
GeodeLink™ Memory Controller
AMD Geode™ GX Processors Data Book
Architecture Overview