AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 152

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

5.5.2.57 Default Region Configuration Properties Register
MSR Address
Type
Reset Value
Warm Start Value 04xxxxx0_1xxxxx01h
152
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Note: Region Properties: Bits [7:6] = RSVD; Bit 5 = WS; Bit 4 = WC; Bit 3 = WT; Bit 2 = WP; Bit 1 = WA; Bit 0 = CD.
63:56
55:36
35:28
27:8
Bit
Bit
7:0
DEVRP
1
0
See "Region Properties" on page 158 for further details.
ROMRP
Name
MISSER
LDSER
Name
ROMRP
ROMBASE
DEVRP
SYSTOP
SYSRP
00001808h
R/W
01FFFFF0_10000001h
31505E
Data Memory Configuration Bit Descriptions (Continued)
Default Region Configuration Properties Bit Descriptions
Default Region Configuration Properties Register Map
Description
Serialize Load Misses. Stall everything but snoops on a load miss. If any part of the PCI
space is marked as cacheable, set this bit. Data accesses are made from the cacheable
space, and there is a PCI master device that must complete a master request before it
completes a slave read.
0: Load misses are treated the same as load hits.
1: Load misses prevent non-snoop requests from being handled until the miss data is
Serialize Loads vs Stores. All loads are serialized versus stores in the store queue, but
a load that hits the DCache completes without affecting any pending stores in the write
buffers.
0: Loads can bypass stores based on region properties.
1: All loads and stores are executed in program order.
Description
ROM Region Properties. Region properties for addresses greater than ROMBASE (bits
55:36]).
ROM Base Address. Base address for boot ROM. This field represents A[32:12] of the
memory address space, 4 KB granularity.
SYSTOP to ROMBASE Region Properties. Region properties for addresses less than
ROMBASE (bits 55:36]) and addresses greater than or equal to SYSTOP (bits [27:8]).
Top of System Memory. Top of system memory that is available for general processor
use. The frame buffer and other private memory areas are located above SYSTOP.
System Memory Region Properties. Region properties for addresses less than SYS-
TOP (bits [27:8]). Note that Region Configuration 000A0000h-000FFFFFh takes prece-
dence over SYSRP.
returned by the BC.
SYSTOP
ROMBASE
AMD Geode™ GX Processors Data Book
9
8
CPU Core Register Descriptions
7
6
5
SYSRP
4
3
DEVRP
2
1
0