HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 85

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
Table 174. LN2_CFG_0 register (address 00h) bit description
Default settings are shown highlighted.
Table 175. LN2_CFG_1 register (address 01h) bit description
Default settings are shown highlighted.
Table 176. LN2_CFG_2 register (address 02h) bit description
Default settings are shown highlighted.
Table 177. LN2_CFG_3 register (address 03h) bit description
Default settings are shown highlighted.
Table 178. LN2_CFG_4 register (address 04h) bit description
Default settings are shown highlighted.
Table 179. LN2_CFG_5 register (address 05h) bit description
Default settings are shown highlighted.
Table 180. LN2_CFG_6 register (address 06h) bit description
Default settings are shown highlighted.
Table 181. LN2_CFG_7 register (address 07h) bit description
Default settings are shown highlighted.
DAC1408D650
Product data sheet
Bit
7 to 0
Bit
3 to 0
Bit
4 to 0
Bit
7
4 to 0
Bit
7 to 0
Bit
4 to 0
Bit
7 to 0
Bit
7 to 6
4 to 0
Symbol
LN2_DID[7:0]
Symbol
LN2_BID[3:0]
Symbol
LN2_LID[4:0]
Symbol
LN2_SCR
LN2_L[4:0]
Symbol
LN2_F[7:0]
Symbol
LN2_K[4:0]
Symbol
LN2_M[7:0]
Symbol
LN2_CS[1:0]
LN2_N[4:0]
10.15.2.14 Page 7 bit definition detailed description
Please refer to
tables, all the values emphasized in bold are the default values.
Table 173
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 November 2010
Access
R
Access
R
Access
R
Access
R
R
Access
R
Access
R
Access
R
Access
R
R
for a register overview and their default values. In the following
Value
-
Value
-
Value
-
Value
-
-
Value
Value
-
Value
-
Value
-
-
-
2, 4 or 8 interpolating DAC with JESD204A
Description
lane 2 device ID
Description
lane 2 bank ID
Description
lane 2 lane ID
Description
scrambling on
number of lanes minus 1
Description
Description
number of frames per multiframe minus 1
Description
number of converters per device minus 1
Description
number of control bits
converter resolution minus 1
number of octets per frame minus 1
DAC1408D650
© NXP B.V. 2010. All rights reserved.
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