HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 15

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
DAC1408D650
Product data sheet
10.2.5.1 Single device operation
10.2.5.2 Multi-device operation
10.2.4 Descrambler
10.2.5 inter-lane alignment
The descrambler is a 16-bit parallel self-synchronous descrambler based on the
polynomial
This feature removes strict PCB design skew compensation between the lanes.
This module handles the alignment of the four data streams. Because of inter-lane skew
and each PLL per lane concept, these alignment characters may be received at different
times by the receivers. After the synchronization period, the lock signal is high. This
enables the receipt of K28.3 /A/ characters.
The /A/ characters provided in the initial alignment sequence are used to align the four
data streams. The ILA_CNTRL register’s SEL_ILA[1:0] bits select which K28.3 /A/ symbol
triggers the initial lane alignment:“00” = 1st /A/ symbol, “01” = 2nd /A/ symbol,
“10” = 3rd /A/ symbol, “11” = 4th /A/ symbol;
have received their first selected /A/, they start propagating the received data to the frame
assembly module at the same point in time.
This module can compensate for up to 7 frame clock period misalignments between the
lanes.
When initial lane alignment is not supported, the manual alignment mode can be used.
After the initial ILA sequence, the lane alignment monitoring starts. If the received user
data contains a K28.3 /A/ symbol:
DAC1408D650 implements a multi-device inter-lane alignment that guarantees a skew of
less than one output period between them.
Two modes are available: master/slave and all slave. Both make use of the MDS_P and
MDS_N pins.
•
•
•
its position is compared to the value of the alignment monitor counter
if two successive K28.3 /A/ symbols have been received at a wrong position, a
realignment takes place
if the buffers are empty or overflow, this is indicated by the registers
ILA_BUF_ERR_LN0 to ILA_BUF_ERR_LN3
1
+
x
All information provided in this document is subject to legal disclaimers.
14
+
x
15
Rev. 4 — 26 November 2010
. This processing can be turned off.
2, 4 or 8 interpolating DAC with JESD204A
Table 86 on page
DAC1408D650
61. When all receivers
© NXP B.V. 2010. All rights reserved.
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