HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet

HSDC-JAKIT1W2/DB

Manufacturer Part Number

HSDC-JAKIT1W2/DB

Description

DAC/ADC LATTICE KIT

Manufacturer

NXP Semiconductors

Series

-r

Datasheets

1.ADC1413D125HNC15.pdf (43 pages)

2.DAC1408D650HNC15.pdf (98 pages)

3.HSDC-JAKIT1W2DB.pdf (2 pages)

4.HSDC-JAKIT1W2DB.pdf (2 pages)

5.HSDC-JAKIT1W2DB.pdf (3 pages)

Specifications of HSDC-JAKIT1W2/DB

Main Purpose

Interface, ADC/DAC for Lattice ECP3 FPGA

Embedded

Yes, FPGA / CPLD

Utilized Ic / Part

ADC1413D, DAC1408D, ECP3 FPGA

Primary Attributes

Loop Back Demo with 2 High Speed Converters

Secondary Attributes

USB Powered

Lead Free Status / Rohs Status

Lead free / RoHS Compliant

Other names

568-6898

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Dual-channel ADCs with JESD204A-compliant

outputs for wireless and industrial

NXP advanced dual channel ADC integrates a two-lane CGV™ serial interface, JEDEC JESD204A-

compliant, optimized for high-speed applications.

Key features

} SNR: 71.6 dB typical, SFDR: 89 dBc typical

} Maximum sample rate: up to 65, 80, 105, or 125 Msps

} Dual-channel - 11, 12, 14 and 16-bit resolution - pipelined

} Two highly configurable JEDEC JESD204A-compliant CGV™

} SPI control/status interface

} HVQFN56 package

Applications

} Wireless and wired broadband communications, especially

} Wideband spectral analysis

} Industrial imaging systems

} Medical equipment

} Instrumentation

ADC core with dual-stage linearity calibration

serial output lanes

multicarrier standards

NXP dual 11, 12, 14, 16 bits ADC

ADC1113D series

ADC1213D series

ADC1413D series

ADC1613D series

The NXP ADC1413D series comprises dual-channel

analog-to-digital converters (ADCs) that support serial digital

transmission in compliance with the new JEDEC JESD204A

interface standard. Only one CGV™ transmitter per channel is

necessary to support sample rates of 125 Msps and to carry out

16-bit resolution.

CGV™ (Convertisseur Grande Vitesse) designates NXP’s

compliant, superset implementation of the JEDEC JESD204A

interface standard, with enhanced rate (4.0 Gbps typical),

enhanced reach (100 cm typical), enhanced features (multiple

DAC synchronization) and assured FPGA interoperability.

Specifically, NXP offers enhancements in terms of transceiver

rate (up to 4.0 Gbps versus the standard rate of 3.125 Gbps, a

28% increase), and transmitter reach (up to 100 cm versus the

standard reach of 20 cm, a 400% increase).

The ADCs maintain excellent dynamic performances from

baseband to input frequency up to 600 MHz, making them ideal

for applications in communications, industrial imaging, and

medical equipment.

The ADCs operate from a single 3-V supply for the analog

circuitry and a 1.8-V supply for the digital output drivers.

Related parts for HSDC-JAKIT1W2/DB

HSDC-JAKIT1W2/DB Summary of contents

Page 1

Dual-channel ADCs with JESD204A-compliant outputs for wireless and industrial NXP advanced dual channel ADC integrates a two-lane CGV™ serial interface, JEDEC JESD204A- compliant, optimized for high-speed applications. Key features } SNR: 71.6 dB typical, SFDR: 89 dBc typical } Maximum ...

Page 2

The addition of a Serial Peripheral Interface (SPI) makes the ADCs and their JEDEC serial output modes easy to configure and monitor. All these products and versions are pin to pin compatible which allows easy upgrade in end application. ADC1413D ...

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