HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 43

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
Table 30.
Default settings are shown highlighted.
Table 31.
Table 32.
Table 33.
Default settings are shown highlighted.
Table 34.
Default settings are shown highlighted.
Table 35.
Default settings are shown highlighted.
DAC1408D650
Product data sheet
Bit
7
6
5 to 0
Bit
7 to 6
5 to 0
Bit
7 to 6
5 to 0
Bit
1
0
Bit
3 to 1
Bit
3 to 1
Symbol
DAC_B_PD
DAC_B_SLEEP
DAC_B_OFFSET[5:0]
Symbol
DAC_B_GAIN_COARSE[1:0]
DAC_B_GAIN_FINE[5:0]
Symbol
DAC_B_GAIN_COARSE[3:2]
DAC_B_OFFSET[11:6]
Symbol
MINUS_3DB
NOISE_SHAPER
Symbol
DAC_DIG_BIAS[2:0]
Symbol
DAC_MST_BIAS[2:0]
DAC_B_CFG_1 register (address 0Ch) bit description
DAC_B_CFG_2 register (address 0Dh) bit description
DAC_B_CFG_3 register (address 0Eh) bit description
DAC_CFG register (address 0Fh) bit description
DAC_CURRENT_0 register (address 11h) bit description
DAC_CURRENT_1 register (address 12h) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 November 2010
Access
R/W
R/W
R/W
Access
R/W
R/W
Access
R/W
R/W
Access
R/W
R/W
Access
R/W
Access
R/W
Value
0
1
0
1
00h
Value
1h
00h
Value
3h
00h
Value
0
1
0
1
Value
3h
Value
3h
2, 4 or 8 interpolating DAC with JESD204A
Description
DAC B power
DAC B Sleep mode
lower 6 bits for the DAC B offset
Description
least significant 2 bits for the DAC B gain setting for
coarse adjustment
the 6 bits for the DAC B gain setting for fine
adjustment
Description
most significant 2 bits for the DAC B gain setting for
coarse adjustment
most significant 6 bits for the DAC B offset
Description
NCO gain
noise shaper
Description
bias current control (see
Description
bias current control (see
on
off
disabled
enabled
unity
3 dB
disabled
enabled
DAC1408D650
Table
Table
46)
46)
© NXP B.V. 2010. All rights reserved.
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