HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet

HSDC-JAKIT1W2/DB

Manufacturer Part Number

HSDC-JAKIT1W2/DB

Description

DAC/ADC LATTICE KIT

Manufacturer

NXP Semiconductors

Series

-r

Datasheets

1.ADC1413D125HNC15.pdf (43 pages)

2.DAC1408D650HNC15.pdf (98 pages)

3.HSDC-JAKIT1W2DB.pdf (2 pages)

4.HSDC-JAKIT1W2DB.pdf (2 pages)

5.HSDC-JAKIT1W2DB.pdf (3 pages)

Specifications of HSDC-JAKIT1W2/DB

Main Purpose

Interface, ADC/DAC for Lattice ECP3 FPGA

Embedded

Yes, FPGA / CPLD

Utilized Ic / Part

ADC1413D, DAC1408D, ECP3 FPGA

Primary Attributes

Loop Back Demo with 2 High Speed Converters

Secondary Attributes

USB Powered

Lead Free Status / Rohs Status

Lead free / RoHS Compliant

Other names

568-6898

Current page: 1 of 2
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JESD204A-compliant D/A conversion for

wideband communication & instrumentation

Optimized for high-speed applications, such as 2.5/3/4G wireless, video broadcast, and

instrumentation, this advanced DAC has selectable interpolating filters and a four-lane CGV™

serial interface, and complies with the new JEDEC JESD204A.

Key features

} Dual-channel, 10, 12, 14 bit resolution

} 650 and 750 Msps maximum output rate

} Four-lane JEDEC JESD204A serial digital input

} 32 bit programmable NCO frequency synthesizer

} SPI control/status interface

} HVQFN64 package

} MDS (Multi-DAC Synchronisation)

} Interpolation filters : 2x, 4x, 8x

Applications

} Wireless infrastructure: Multicarrier GSM, EDGE, CDMA,

} Multipoint communication infrastructure: LMDS/MMDS

} Broadband wireless systems

} Digital radio links

} High-speed instrumentation

} Automated Test Equipment (ATE)

} Video broadcast equipment

with low-power option

WCDMA, TD-SCDMA, WiMAX, LTE

NXP dual-channel 10, 12, 14 bits,

up to 750 Msps D/A converter

DAC1408D series

The NXP DAC1408D series, 14 bit digital-to-analog converters

with two channels, are equipped with interpolation filters

selectable as 2x, 4x, or 8x. It is a high-speed solution optimized

for a variety of advanced applications, including single- and

multi-carrier wireless infrastructure transmitter signals.

It is available in three resolutions, 10, 12 and 14-bit and

supports maximum output sample rates up to 650 and 750 Msps

It uses fully configurable digital on-chip modulation to manage

I and Q inputs, up-converting them from baseband to IF. The

mixing frequency is adjusted, via an SPI (Serial Peripheral

Interface) interface with a 32 bit NCO (Numerically Controlled

Oscillator). The phase is controlled by a 16 bit register.

Integrated IQ phase compensation, IQ gain matching and DC

offset correction features ease DAC to Analog Quadrature

Modulator interconnection.

Supporting input data rates up to 312.5 Msps as well as polarity

and lane swapping, the DAC1408D series has fourlane CGV™

receivers.

CGV™ (Convertisseur Grande Vitesse) designates NXP’s

compliant, superset implementation of the JEDEC JESD204A

Related parts for HSDC-JAKIT1W2/DB

HSDC-JAKIT1W2/DB Summary of contents

Page 1

JESD204A-compliant D/A conversion for wideband communication & instrumentation Optimized for high-speed applications, such as 2.5/3/4G wireless, video broadcast, and instrumentation, this advanced DAC has selectable interpolating filters and a four-lane CGV™ serial interface, and complies with the new JEDEC JESD204A. ...

Page 2

Gbps typical), enhanced reach (100 cm typical), enhanced features (multiple DAC synchronization) and assured FPGA interoperability. Specifically, NXP offers enhancements in terms of transceiver rate (up to 4.0 Gbps versus the standard rate of ...

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