HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 21

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
DAC1408D650
Product data sheet
10.2.6 Frame assembly
DAC1408D650 supports only /F/ = 1, which means that every frame clock period carries
one byte per lane. Frame assembly combines the octet of lane_0 with the six MSB bits of
lane_1 and reassembles the original 14-bit sample. The same is done for lane_2 and
lane_3. Tail bits are dropped.
The frame assembler also handles previously triggered errors.
If scrambling is enabled:
If scrambling is disabled:
If a nit_err (not-in-table error) or kout_unexp (unexpected control character) occurs in
lane_0 and/or lane_1, the previous 14-bit sample is repeated twice for I (lane_0,
lane_1). The same is done for Q (lane_2, lane_3).
If a nit_err (not-in-table error) or kout_unexp (unexpected control character) occurs in
lane_0 and/or lane_1, the previous 14-bit sample is repeated once for I (lane_0,
lane_1). The same is done for Q (lane_2, lane_3).
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 November 2010
2, 4 or 8 interpolating DAC with JESD204A
DAC1408D650
© NXP B.V. 2010. All rights reserved.
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