HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 51

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

Table 59.
Address Register name
0
3
4
5
6
7
8
9
22 16h SET_VCM_VOLTAGE R/W
23 17h SET_SYNC
27 1Bh TYPE_ID
28 1Ch DAC_VERSION
29 1Dh DIG_VERSION
30 1Eh JRX_ANA_VERSION R
31 1Fh PAGE_ADDRESS
00h MAINCONTROL
03h JCLK_CNTRL
04h RST_EXT_FCLK
05h RST_EXT_DCLK
06h DCSMU_PREDIVCNT R/W
07h PLL_CHARGETIME
08h PLL_RUN_IN_TIME
09h CA_RUN_IN_TIME
10.15.2.5 Page 2 allocation map description
Page 2 register allocation map
R/W Bit definition
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
b7
SR_CDI
DAC
-
-
-
-
b6
FRONTEND[1:0]
-
-
-
-
SET_SYNC_VCOM[2:0]
b5
FULL_RE_
INIT
CDI_MODE[1:0]
-
-
JRX_ANA_VERSION_ID[7:0]
RST_EXT_DCLK_TIME[7:0]
b4
RST_EXT_FCLK_TIME[7:0]
DCSMU_PREDIVIDER[7:0]
SYNC_INIT_
PLL_CHARGE_TIME[7:0]
DAC_VERSION_ID[7:0]
PLL_RUNIN_TIME[7:0]
DIG_VERSION_ID[7:0]
CA_RUNIN_TIME[7:0]
LEVEL
DUAL
-
-
b3
0
-
-
-
DSP
b2
FCLK_POL
SET_VCM[3:0]
SET_SYNC_LEVEL[2:0]
0
PAGE[2:0]
b1
FORCE_
RESET_
DCLK
FCLK_SEL[1:0]
BIT_RES[1:0]
b0
FORCE_
RESET_
FCLK
Default
Bin
00000011 03h
00000000 00h
00111111 3Fh
00100000 20h
00011110 1Eh
00110010 32h
00110010 32h
00000100 04h
00000010 02h
01000011 43h
11011101 DDh
00000001 01h
00000010 02h
00000010 02h
00000000 00h
Hex