HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 12

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
DAC1408D650
Product data sheet
Fig 3.
SYNC_OUT
lane#
The descrambler can be enabled/disabled
JESD204A receiver
DES
10.2 JESD204A receiver
10b
This device is MCDA-ML compliant, offering inter-lane alignment between several
devices. Samples alignment between devices is maintained up to output level because of
an NXP proprietary mechanism. One device is configured as the master and all the others
are configured as slaves. These align their output samples automatically to the master
ones. Therefore, a system with several DAC1408D650s can produce data with a
guaranteed alignment of less than 1 DAC output clock period.
Each DAC generates two complementary current outputs on pins IOUTAP/IOUTAN and
IOUTBP/IOUTBN. This provides a full-scale output current of up to 20 mA. An internal
reference is available for the reference current which is externally adjustable using pin
VIRES.
The DAC1408D650 must be configured before operating. Therefore, it features an SPI
slave interface to access internal registers. Some of these registers also provide
information about the JESD204A interface status.
The DAC1408D650 requires supplies of both 3.3 V and 1.8 V. The 1.8 V supply has
separate digital and analog power supply pins. The clock input is LVDS compliant.
The JEDEC204A defines the following parameters:
The DAC1408D650 supports both LMF = 421 and LMF = 211. The current setting is
configurable via the SPI registers interface.
The complete Digital Layer Processing (DLP) adds a variable delay on each lane path.
This is mainly because of the inter-lane alignment.
Table 6.
[1]
[2]
Symbol Parameter
t
d
CLOCK
ALIGN
frame
clock
D = guaranteed by design.
Frame clock cycle.
10b
delay time
Digital Layer Processing Latency
L is the number of lanes per link
M is the number of converters per device
F is the number of bytes per frame clock period
WORD
ALIGN
SYNC
All information provided in this document is subject to legal disclaimers.
AND
Rev. 4 — 26 November 2010
Conditions
digital layer processing
delay
10b
K-DETECT
10b/8b
RX CONTROLLER
8b
2, 4 or 8 interpolating DAC with JESD204A
DESCRAMBLER
Test
D
[1]
8b
Min
13
DAC1408D650
Typ
-
8b
8b
8b
8b
© NXP B.V. 2010. All rights reserved.
Max
28
14b
14b
configuration
interface
internal
001aak161
Unit
cycle
12 of 98
[2]