HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 18

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
DAC1408D650
Product data sheet
The MDS signal generated by the master DAC must reach all slaves within one DAC
output clock period. This induces PCB layout constraints for the MDS signal and also for
the clock distribution. Because trace lengths differ, the clock edges reach each of the
DACs at different times.
The worst case clock skew is given by
sum of the trace delay and the clock skew at the output of the clock generator.
The maximum allowable trace delay for the MDS signal is given by
Fig 9.
Clock skew case 1: Master is farthest
slave 1 clock
slave 2 clock
master clock
All information provided in this document is subject to legal disclaimers.
ref clock
Rev. 4 — 26 November 2010
PH03
PH02
t
PH01
2, 4 or 8 interpolating DAC with JESD204A
1
TDAC
=
PH01 PH03
–
DAC1408D650
, where PH0x represents the
t
001aal072
=
© NXP B.V. 2010. All rights reserved.
TDAC t
–
18 of 98
1
.