HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 17
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
HSDC-JAKIT1W2/DB
Manufacturer Part Number
HSDC-JAKIT1W2/DB
Description
DAC/ADC LATTICE KIT
Manufacturer
NXP Semiconductors
Series
-r
Datasheets
1.ADC1413D125HNC15.pdf
(43 pages)
2.DAC1408D650HNC15.pdf
(98 pages)
3.HSDC-JAKIT1W2DB.pdf
(2 pages)
4.HSDC-JAKIT1W2DB.pdf
(2 pages)
5.HSDC-JAKIT1W2DB.pdf
(3 pages)
Specifications of HSDC-JAKIT1W2/DB
Main Purpose
Interface, ADC/DAC for Lattice ECP3 FPGA
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
ADC1413D, DAC1408D, ECP3 FPGA
Primary Attributes
Loop Back Demo with 2 High Speed Converters
Secondary Attributes
USB Powered
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6898
- ADC1413D125HNC15 PDF datasheet
- DAC1408D650HNC15 PDF datasheet #2
- HSDC-JAKIT1W2DB PDF datasheet #3
- HSDC-JAKIT1W2DB PDF datasheet #4
- HSDC-JAKIT1W2DB PDF datasheet #5
- Current page: 17 of 98
- Download datasheet (3Mb)
NXP Semiconductors
DAC1408D650
Product data sheet
10.2.5.3 Master/slave mode
The external reference is provided by one of the DACs (the master DAC), which has to be
configured to do this. The others are set to slave mode.
Fig 8.
TX
Master-slave mode
All information provided in this document is subject to legal disclaimers.
SYNC_0
SYNC_1
SYNC_2
Rev. 4 — 26 November 2010
DIG
DIG
DIG
ref_A
ref_A
ref_A
BUFFER
BUFFER
BUFFER
2, 4 or 8 interpolating DAC with JESD204A
MGMT
MGMT
MGMT
COMP
COMP
COMP
CLK
CLK
CLK
mds_out
mds_out
mds_out
mds_in
mds_in
mds_in
Q
Q
Q
I
I
I
DAC
DAC
DAC
DISTRIBUTION
DAC1408D650
CLOCK
© NXP B.V. 2010. All rights reserved.
MASTER
SLAVE
SLAVE
DAC 0
DAC 1
DAC 2
REF_CLOCK
001aal070
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