HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 57

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

Table 78.
Address Register name
18 12h INIT_SCR_
19 13h INIT_SCR_
20 14h INIT_SCR_
21 15h INIT_SCR_
22 16h INIT_SCR_
23 17h INIT_SCR_
24 18h INIT_SCR_
25 19h INIT_ILA_
26 1Ah INIT_ILA_
27 1Bh ERROR_
28 1Ch REINIT_CNTRL
31 1Fh PAGE_ADDRESS R/W
S7T1_LN0
S15T8_LN1
S7T1_LN1
S15T8_LN2
S7T1_LN2
S15T8_LN3
S7T1_LN3
BUFPTR_LN01
BUFPTR_LN23
HANDLING
Page 4 register allocation map
R/W Bit definition
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
b7
ILA_LN3
REINIT_
-
-
-
-
-
-
…continued
INIT_ILA_BUFPTR_LN1[3:0]
INIT_ILA_BUFPTR_LN3[3:0]
b6
NAD_ERR_
REINIT_ILA
CORR
_LN2
-
b5
REINIT_ILA_
KUX_CORR NAD_CORR
LN1
-
INIT_VALUE_S15_S8_LN2[7:0]
INIT_VALUE_S15_S8_LN3[7:0]
INIT_VALUE_S15_S8_LN1[7:0]
b4
REINIT_ILA_
LN0
INIT_VALUE_S7_S1_LN0[6:0]
INIT_VALUE_S7_S1_LN1[6:0]
INIT_VALUE_S7_S1_LN2[6:0]
INIT_VALUE_S7_S1_LN3[6:0]
-
b3
RESYNC_O
_L_LN3
CORR_MODE[1:0]
-
INIT_ILA_BUFPTR_LN0[3:0]
INIT_ILA_BUFPTR_LN2[3:0]
b2
RESYNC_O
_L_LN2
b1
RESYNC_O
IMPL_ALT
PAGE[2:0]
_L_LN1
b0
RESYNC_O
IGNORE_
_L_LN0
ERR
Default
Bin
00000000 00h
00000000 00h
00000000 00h
00000000 00h
00000000 00h
00000000 00h
00000000 00h
10001000 88h
10001000 88h
00000000 00h
00000000 00h
00000000 00h
Hex