HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 67

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
Table 106. REINIT_CNTRL register (address 1Ch) bit description
Default settings are shown highlighted.
Table 107. PAGE_ADDRESS register (address 1Fh) bit description
DAC1408D650
Product data sheet
Bit
3
2
1
0
Bit
2 to 0
Symbol
RESYNC_O_L_LN3
RESYNC_O_L_LN2
RESYNC_O_L_LN1
RESYNC_O_L_LN0
Symbol
PAGE[2:0]
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 November 2010
Access
R/W
R/W
R/W
R/W
Access
R/W
Value
0
1
0
1
0
1
0
1
Value
0h
2, 4 or 8 interpolating DAC with JESD204A
…continued
Description
lane 3, resync over link
Description
page_address
lane 2, resync over link
lane 1, resync over link
lane 0, resync over link
no action
lane 3 lane controller checks for
K28.5 /K/ symbols
no action
lane 2 lane controller checks for
K28.5 /K/ symbols
no action
lane 1 lane controller checks for
K28.5 /K/ symbols
no action
lane 0 controller checks for K28.5 /K/ symbols
DAC1408D650
© NXP B.V. 2010. All rights reserved.
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