HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 24

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HSDC-JAKIT1W2/DB

Manufacturer Part Number
HSDC-JAKIT1W2/DB
Description
DAC/ADC LATTICE KIT
Manufacturer
NXP Semiconductors
Series
-r

Specifications of HSDC-JAKIT1W2/DB

Main Purpose
Interface, ADC/DAC for Lattice ECP3 FPGA
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
ADC1413D, DAC1408D, ECP3 FPGA
Primary Attributes
Loop Back Demo with 2 High Speed Converters
Secondary Attributes
USB Powered
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6898
NXP Semiconductors
DAC1408D650
Product data sheet
10.3.2 SPI timing description
The SPI interface can operate at a frequency of up to 15 MHz. The SPI timing is shown in
Figure
The SPI timing characteristics are given in
Table 9.
Symbol
f
t
t
t
t
t
t
SCLK
w(SCLK)
su(SCS_N)
h(SCS_N)
su(SDIO)
h(SDIO)
w(RESET_N)
Fig 14. SPI timing diagram
RESET_N
SCS_N
14.
SCLK
SDIO
SPI timing characteristics
Parameter
SCLK frequency
SCLK pulse width
SCS_N set-up time
SCS_N hold time
SDIO set-up time
SDIO hold time
RESET_N pulse width
All information provided in this document is subject to legal disclaimers.
50 %
50 %
50 %
Rev. 4 — 26 November 2010
t
w(RESET_N)
50 %
t
t
su(SCS_N)
su(SDIO)
t
h(SDIO)
2, 4 or 8 interpolating DAC with JESD204A
Table
Min
-
30
20
20
10
5
30
9.
t
w(SCLK)
DAC1408D650
Typ
-
-
-
-
-
-
-
Max
15
-
-
-
-
-
-
© NXP B.V. 2010. All rights reserved.
t
h(SCS_N)
001aaj813
Unit
MHz
ns
ns
ns
ns
ns
ns
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