HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 52

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HSDC-JAKIT1W2/DB

Manufacturer Part Number
HSDC-JAKIT1W2/DB
Description
DAC/ADC LATTICE KIT
Manufacturer
NXP Semiconductors
Series
-r

Specifications of HSDC-JAKIT1W2/DB

Main Purpose
Interface, ADC/DAC for Lattice ECP3 FPGA
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
ADC1413D, DAC1408D, ECP3 FPGA
Primary Attributes
Loop Back Demo with 2 High Speed Converters
Secondary Attributes
USB Powered
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6898
NXP Semiconductors
Table 60.
Default settings are shown highlighted.
Table 61.
Default settings are shown highlighted.
DAC1408D650
Product data sheet
Bit
5
4
3
2
1
0
Bit
7
5 to 4
2
1 to 0
Symbol
FULL_RE_INIT
SYNC_INIT_LEVEL
-
-
FORCE_RESET_DCLK
FORCE_RESET_FCLK
Symbol
SR_CDI
CDI_MODE[1:0]
FCLK_POL
FCLK_SEL[1:0]
10.15.2.6 Page 2 bit definition detailed description
MAINCONTROL register (address 00h) bit description
JCLK_CNTRL register (address 03h) bit description
Please refer to
tables, all the values emphasized in bold are the default values.
Table 59
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 November 2010
Access
R/W
R/W
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
for a register overview and their default values. In the following
Value
0
1
0
1
0
1
0
1
Value
0
1
00
01
10
11
0
1
00
01
10
11
2, 4 or 8 interpolating DAC with JESD204A
Description
initialization
synchronization
must be written with ’0’
must be written with ’0’
reset_fclk
Description
cdi reset
cdi mode
f
reset_dclk
f
clk
clk
quick reinitialization
full reinitialization
synchronization starts with '0'
synchronization starts with '1'
release reset_dclk
force reset_dclk
release reset_fclk
force reset_fclk
no action
soft reset cdi
cdi_mode 0 (^2 modes)
cdi_mode 1 (^4 modes)
cdi_mode 2 (^8 modes)
reserved
no action
invert polarity
dclk  2
dclk
dclk_div2; running
dclk_div2; reset dclk_div2 divider
polarity
clock source
DAC1408D650
© NXP B.V. 2010. All rights reserved.
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