PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 91

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit
1
2
3
4
5
6
7
Function
Posted Write
with Parity Error
Posted Write
with Non-
Delivery Data
Target Abort
During Posted
Write
Master Abort
During Posted
Write
Delayed Write
with Non-
Delivery
Delayed Read
Without Data
From Target
Reserved
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/O
Page 91 of 114
Description
0: P_SERR# is asserted if a parity error is detected on the target bus
during a posted write transaction and the SERR# enable bit in the
command register is set.
1: P_SERR# is not asserted, although a parity error is detected on the
target bus during a posted write transaction and the SERR# enable bit in
the command register is set.
Reset to 0
0: P_SERR# is asserted if the bridge is not able to transfer any posted
write data after 2
register is set.
1: P_SERR# is not asserted although the bridge is not able to transfer any
posted write data after 2
command register is set.
Reset to 0
0: P_SERR# is asserted if the bridge receives a target abort when
attempting to deliver posted write data and the SERR# enable bit in the
command register is set.
1: P_SERR# is not asserted even though the bridge receives a target
abort when attempting to deliver posted write data and the SERR# enable
bit in the command register is set.
Reset to 0
0: P_SERR# is asserted if the bridge receives a master abort when
attempting to deliver posted write data and the SERR# enable bit in the
command register is set.
1: P_SERR# is not asserted even though the bridge receives a master
abort when attempting to deliver posted write data and the SERR# enable
bit in the command register is set.
Reset to 0
0: P_SERR# is asserted if the bridge is not able to transfer any delayed
write data after 2
register is set.
1: P_SERR# is not asserted even though the bridge is not able to transfer
any delayed write data after 2
command register is set.
Reset to 0
0: P_SERR# is asserted if the bridge is not able to transfer any read data
from the target after 2
command register is set.
1: P_SERR# is not asserted even though the bridge is not able to transfer
and read data from the target after 2
in the command register is set.
Reset to 0.
Returns 0 when read. Reset to 0.
24
24
attempts and the SERR# enable bit in the command
attempts and the SERR# enable bit in the command
24
24
attempts and the SERR# enable bit in the
attempts and the SERR# enable bit in the
24
attempts and the SERR# enable bit in the
24
attempts and the SERR# enable bit
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A