PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 83

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.21
14.1.22
14.1.23
14.1.24
14.1.25
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET
24h
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS
REGISTER – OFFSET 28h
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS
REGISTER – OFFSET 2Ch
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
Bit
19:16
31:20
Bit
31:0
Bit
31:0
Bit
15:0
Bit
31:16
Prefetchable
Function
64-bit addressing
Memory Limit
Address [31:20]
Function
Prefetchable
Memory Base
Address, Upper
32-bits [63:32]
Function
Prefetchable
Memory Limit
Address, Upper
32-bits [63:32]
Function
I/O Base
Address, Upper
16-bits [31:16]
Function
I/O Limit
Address, Upper
16-bits [31:16]
Type
R/O
R/W
Type
R/W
Type
R/W
Type
R/W
Type
R/W
Page 83 of 114
Description
Indicates 64-bit addressing
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 1
Defines the top address of an address range for the bridge to determine
when to forward memory read and write transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20] and are
writable. The lower 20 bits are assumed to be FFFFFh.
Description
Defines the upper 32-bits of a 64-bit bottom address of an address range
for the bridge to determine when to forward memory read and write
transactions from one interface to the other.
Reset to 0
Description
Defines the upper 32-bits of a 64-bit top address of an address range for
the bridge to determine when to forward memory read and write
transactions from one interface to the other.
Reset to 0
Description
Defines the upper 16-bits of a 32-bit bottom address of an address range
for the bridge to determine when to forward I/O transactions from one
interface to the other.
Reset to 0
Description
Defines the upper 16-bits of a 32-bit top address of an address range for
the bridge to determine when to forward I/O transactions from one
interface to the other.
Reset to 0
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A